Abstract: An integrated device comprises an epitaxial layer forming a first and a second region separated by at least one air gap. The first region forms, for example, a suspended mass of an accelerometer. A bridge element extends on the air gap and has a suspended electrical connection line electrically connecting the first and the second region and a protective structure of etch-resistant material, which surrounds the electrical connection line on all sides. The protective structure is formed by a lower portion of silicon nitride and an upper portion of silicon carbide, the silicon carbide surrounding the electrical connection line at the upper and lateral sides.

Abstract: An interface for a data node of a data network including a plurality of data nodes are connected to each other by way of a bus line and activatable in selective manner by address codes transmitted via the bus line. The interface includes an activating address filter allowing addresses intended for the associated data node to be recognized.

Abstract: A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.

Abstract: An inductance structure arranged on a semiconductor substrate, including an inductance and a conductive plane arranged between the inductance and the substrate. The conductive plane is formed of several separate conductive elements, the connection of which is performed by conductive tracks connecting at least one conductive element to a contact point M of the conductive plane. Each of the conductive tracks is arranged so that the resultant of the electromotive forces induced in said conductive track by the inductance is substantially null.

Abstract: The integrated microactuator has a stator and a rotor having a circular extension with radial arms which support electrodes extending in a substantially circumferential direction and interleaved with one another. For the manufacture, first a sacrificial region is formed on a silicon substrate; an epitaxial layer is then grown; the circuitry electronic components and the biasing conductive regions are formed; subsequently a. portion of substrate beneath the sacrificial region is removed, forming an aperture extending through the entire substrate; the epitaxial layer is excavated to define and separate from one another the rotor and the stator, and finally the sacrificial region is removed to release the mobile structures from the remainder of the chip.

Abstract: A multilevel memory stores words formed by a plurality of binary subwords in a plurality of cells, each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors divided into sector blocks, and are selected via a global row decoder, a global column decoder, and a plurality of local row decoders, which simultaneously supply a ramp voltage to a biasing terminal of the selected cells. Threshold reading comparators are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches, are arranged between the global word lines and local word lines, opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.

Abstract: A process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion, providing for: over a semiconductor substrate, insulatively placing a silicidated polysilicon layer that includes a polysilicon layer selectively doped in accordance to a conductivity type of at least the high-performance logic integrated circuit components, covered by a silicide layer; selectively covering the silicidated polysilicon layer with a hard mask; defining gate structures for the high-density integrated circuit components and for the high-performance logic integrated circuit components using said hard mask, the gate structures comprising the silicidated polysilicon layer covered with the hard mask; in a dielectric layer formed over the chip, forming contact openings for electrically contacting the high-density integrated circuit components and the high-performance logic integrated circuit com

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.

Abstract: The method comprises the steps of: forming an integrated device including a microactuator in a semiconductor material wafer; forming an immobilization structure of organic material on the wafer; simultaneously forming a securing flange integral with the microactuator and electrical connections for connecting the integrated device to a read/write head; bonding a transducer supporting the read/write head to the securing flange; connecting the electrical connections to the read/write head; cutting the wafer into dices; bonding the microactuator to a suspension; and removing the immobilization structure.

Abstract: An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, this latter enclosed in an isolated region having a second type of conductivity type. The power stage PT comprises a first buried area having the second type of conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The isolation region and the control stage CT comprise respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layers.

Abstract: A simplified non-DSCP process for the definition of the tunnel area in nonvolatile memory cells with semi-conductor floating gates is presented. The memory cells are non-aligned and are incorporated in a matrix of cells and have associated control circuitry. In additional, to each cell a selection transistor is associated. The process includes at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semiconductor; and growth of tunnel oxide. Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Abstract: A byte-switch structure for electrically erasable and programmable non-volatile memories, includes a MOS transistor having a drain electrode coupled to a respective metal control gate line, a source electrode coupled to a respective polysilicon byte control line which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line. The source and drain electrodes of the MOS transistor are respectively a first and a second doped regions of a first conductivity type formed in a semiconductor layer of a second conductivity type at opposite sides of the respective word line.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract: A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Abstract: A method of manufacturing DRAM cells in a substrate, including the steps of: depositing a first conductor in first openings in a first insulator partially exposing source/drain regions; opening a second insulator to partially expose the first openings contacting the source/drain regions, depositing a second conductor, then a third insulator, delimiting in the third insulator and second conductor bit lines of the memory cells, and forming lateral spacers on the sides of the bit lines; opening a fourth insulator to partially expose the first openings in contact with the drain/source regions of the transistors; depositing and etching a third conductor; conformally depositing a dielectric; and depositing a third conductor.