Abstract: The present invention provides a circuit for increasing the noise tolerance of a receiving gate. This is accomplished by separating the circuit which sets the positive going threshold, from the circuit which sets the negative going threshold. This eliminates the need of making a design compromise equally suitable to both these threshold requirements. It is achieved by separating the logical drive for switching from a low to a high from the logical drive for switching from a high to a low. Alternate embodiments are presented. In one embodiment, separate drivers for PFET and NFET inverter inputs are employed together with an output latch circuit which prevents the output from being in a floating state. In an alternate embodiment the latch is included in-line with the gate output. An implementation of the invention in a two input AND gate is also described.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.

Abstract: A data string is a sequence of atomic units of data that represent information. In the context of computer data, examples of data strings include executable programs, data files, and boot records consisting of sequences of bytes, or text files consisting of sequences of bytes or characters. The invention solves the problem of automatically constructing a classifier of data strings, i.e., constructing a classifier which, given a string, determines which of two or more class labels should be assigned to it. From a set of (string, class-label) pairs, this invention provides an automated technique for extracting features of data strings that are relevant to the classification decision, and an automated technique for developing a classifier which uses those features to classify correctly the data strings in the original examples and, with high accuracy, classify correctly novel data strings not contained in the example set.

Abstract: In this speech recognition system, the size of the language model is reduced by discarding those n-grams that the acoustic part of the system can recognize most accurately without support from a language model. The n-grams can be discarded dynamically during the running of the system or during the build or setup-time of the system. Trigrams occurring infrequently in the text corpora are substituted for the discarded n-grams to increase the accuracy of the word recognitions.

Abstract: An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.

Abstract: A method and apparatus for using a tree structure to constrain a time-synchronous, fast search for candidate words in an acoustic stream is described. A minimum stay of three frames in each graph node visited is imposed by allowing transitions only every third frame. This constraint enables the simplest possible Markov model for each phoneme while enforcing the desired minimum duration. The fast, time-synchronous search for likely words is done for an entire sentence/utterance. The list of hypotheses beginning at each time frame is stored for providing, on-demand, lists of contender/candidate words to the asynchronous, detailed match phase of decoding.

Abstract: A method and system of recognizing speech. The method and system perform a fast match on a word in the string of speech to be recognized which generates a fast match list representing words in a system vocabulary that most likely match a current word to be recognized. Next, the method and system perform a detailed match on the words in the fast match list and generate a detailed match list representing words that most likely match the current word to be recognized. Then for each word in the detailed match list that can accept a liaison phoneme from a preceding word, where each word is a liaison receptor, adding to the detailed match list a form of the liaison receptor, where the form represents an addition of a liaison phoneme to the liaison receptor, creating a modified detailed match list which is inclusive of the forms of the liaison receptors added to the detailed match list.

Abstract: A method for storing redundant information in an array of data storage devices such that data is protected against two simultaneous storage device failures. The method assigns each data block to two different parity sets, each protected by a different parity block. The protected data blocks and the parity block each reside on a different data storage device.

Abstract: An apparatus for separating an image from a black frame quickly and precisely wherein corner coordinates for a character field are inferred by using a parameter relative to a character frame layout, and more precise corner coordinates are detected by pel distribution in a partial range. The positions of inner walls of a black frame are then inferred by using the detected corner coordinates and the parameter relative to the character frame, and a detection area is set. The positions of the inner walls are precisely detected by the pel distribution in the detection area, and smoothing process is performed on the detected values by employing the detected values of other adjacent black frames. Sequentially, white lines are drawn along the inner walls to separate the black frame from the character, and noise is removed. In consonance with a skew value, the detection area is divided to change the set range, and data separation is performed by using two white lines with a step difference between them.

Abstract: A dictionary based post-processing technique for an on-line handwriting recognition system is described. An input word has all punctuation removed, and the word is checked against a word processing dictionary. If any word matches against the dictionary, it is verified as a valid word. If it does not verify, a stroke match function and a spell-aid dictionary are used to construct a list of possible words. In some cases, the list is appended with possible words based on changing the first character of the originally recognized word. A character-match score, a substitution score and a word length are assigned to the items on the list. A word hypothesis is constructed from the list with each such word being assigned a score. The word with the best score is chosen as the output word for the processor.

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

Abstract: A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

Abstract: A protocol for achieving atomic multicast in a parallel or distributed computing environment. The protocol guarantees concurrency atomicity with a maximum of m-1 message passes among the m server nodes of the system. Under one embodiment of the protocol, an access component message is transferred to the server nodes storing data to be accessed. The first server node of the plurality generates a token to be passed among the accessed nodes. A node can not process its request until it receives the token. A node may pass the token immediately upon ensuring that it is the current expected token.

Abstract: A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.

Abstract: Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.

Abstract: A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications.

Abstract: A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithographic trench opening can be used (1) to improve the cell area, (2) to increase the device length, and (3) to improve the margin of diffusion straps. Acceptable trench capacitance for the cells formed in a single opening can be achieved either by using thin capacitor dielectric, or by expanding the trenches laterally under the devices.

Abstract: This invention is a debugger for HPF-like languages which can be implemented on top of basically any debugger. A primary feature of the debugger is the use of backup breakpoints to generate a program status which is similar to a program status in a sequential execution of the code and the back and forth mapping between processor variables. This debugger requires some new debugging information which must be provided by the compiler. It then allows debugging from a sequential point of view.

Abstract: An antenna is integrated into the laptop to increase the efficiency, convenience and ruggedness of radio frequency transmission. The antenna extends from the laptop's cover when in use for maximum efficiency but retracts when not in use for ruggedness and convenience. The antenna is a multi-modal antenna to permit efficient transmission and reception in more than one range of frequencies. The multi-modal antenna is made up of multiple segments for transmitting and receiving at different frequencies that are matched to a single terminating circuit.