Abstract: A method and apparatus for estimating the probability of phones, a-posteriori, in the context of not only the acoustic feature at that time, but also the acoustic features in the vicinity of the current time, and its use in cutting down the search-space in a speech recognition system. The method constructs and uses a decision tree, with the predictors of the decision tree being the vector-quantized acoustic feature vectors at the current time, and in the vicinity of the current time. The process starts with an enumeration of all (predictor, class) events in the training data at the root node, and successively partitions the data at a node according to the most informative split at that node. An iterative algorithm is used to design the binary partitioning. After the construction of the tree is completed, the probability distribution of the predicted class is stored at all of its terminal leaves.

Abstract: An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Feasible pairs are merged, followed by flattening of the hierarchical graph. The number of I/O pins of the new partition is then reduced, upon which a hierarchical graph is derived. A perturbed partition is then generated, followed by restoration of feasibility.

Abstract: A data string is a sequence of atomic units of data that represent information. In the context of computer data, examples of data strings include executable programs, data files, and boot records consisting of sequences of bytes, or text files consisting of sequences of bytes or characters. The invention solves the problem of automatically constructing a classifier of data strings, i.e., constructing a classifier which, given a string, determines which of two or more class labels should be assigned to it. From a set of (string, class-label) pairs, this invention provides an automated technique for extracting features of data strings that are relevant to the classification decision, and an automated technique for developing a classifier which uses those features to classify correctly the data strings in the original examples and, with high accuracy, classify correctly novel data strings not contained in the example set.

Abstract: A speech synthesis system making use of a pitch-synchronous waveform overlap method to realize stable speech synthesis processing in which pitch shaking is negligible. The present invention is characterized in that glottal closure instants are used as reference points (pitch marks) for overlapping. Since the glottal closure instants can be extracted stably and accurately by using dyadic Wavelet conversion, speech in which pitch shaking is negligible and rumbling sounds are minimized can be synthesized stably. In addition, more flexible waveform separation becomes possible by setting the reference point for overlapping and the reference point for waveform separation to different positions. The extraction of glottal closure instants is performed by searching the local peaks of the dyadic Wavelet conversion, but preferably a threshold value for searching for the local peaks of the dyadic Wavelet conversion is adaptively controlled each time dyadic Wavelet conversion is obtained.

Abstract: A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

Abstract: In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

Abstract: A scheme is presented for storing data on disks in such a way that a checkpoint can easily be taken across several disks connected to different processors in a distributed or parallel computer. A checkpoint can be used to restore the entire disk system to a known state after one or more of the disks or processors fails. When a failure occurs, the disk system is restored to its state at the current checkpoint. The scheme allows significant saving in disk space by requiring that only the data modified since the last checkpoint be copied. The checkpointing algorithm is presented as part of the invention. The invention allows checkpointing of disk space independently of the use of the disk space, for example, in a file system.

Abstract: A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.

Abstract: The invention provides means and methods for extending an instruction-set architecture without impacting the software interface. This circumvents all software compatibility issues, and allows legacy software to benefit from new architectural extensions without recompilation and reassembly. The means employed are a translation engine for translating sequences of old architecture instructions into primary, new architecture instructions, and an extended instruction (EI) cache memory for storing the translations. A processor requesting a sequence of instructions will look first to the EI-cache for a translation, and if translations are unavailable, will look to a conventional cache memory for the sequence, and finally, if still unavailable, will look to a main memory.

Abstract: A method for restoring a computer program infected with a computer virus to its non-viral condition. The method uses certain information about an uninfected host program recorded prior to infection without relying upon pre-existing knowledge of the computer virus. The method includes: recording a checksum of the uninfected original program, the length of the program, and information pertaining to bytes located near the beginning and end of the original program; and, subsequent to any modification of the original program that is deemed suspicious, generating one or more trial reconstructions based on the recorded information and information contained in the modified file; comparing a checksum of each generated trial reconstruction with the checksum of the original program stored in the database; and outputting a trial reconstruction as the original uninfected program if its checksum matches that of the original program.

Abstract: A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

Abstract: A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall leakage, reduces soft errors, eliminates well to substrate leakage, in addition to all the other advantages of SOI devices.

Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.

Abstract: Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.

Abstract: A circuit that can switch between a peak detect and an averaging mode is described. In a preferred embodiment, when the circuit is in a peak detect mode a first transistor is on and a second is off, enabling an amplifier in the circuit to produce a signal representative of the peak value of an input signal. In an averaging mode, the first transistor is off, and a second transistor turns on, disabling the output of the amplifier, and thus enabling the averaging mode components of the invention.

Abstract: This invention is a high performance, standard IO interconnect "bridge" hardware for a parallel machine with a packet switching network in place. Combining new hardware and new software, this bridge connects parallel processors to the external world. The hardware is a "bridge" connecting an internal inter-processor switch to external asynchronous transfer node networks. The software is a "mirror" for making the connections. The invention provides high bandwidth, low latency and deterministic performance, and is inexpensive to build.

Abstract: A method for using information provided during error correction for modifying character prototypes in an on-line handwriting recognition system is disclosed. The method allows a user to correct misrecognized handwritten characters by overwriting directly on the displayed ASCII representation of the recognition result for a given character. The rewritten character is then used to silently retrain the system so as to adapt it to the user's particular handwriting style.

Abstract: A latch circuit. The circuit includes a static digital logic circuit, comprising a multiplexer having a plurality of static input data lines and one or more select lines for selecting data from one of the input lines as multiplexer output data; latching means for latching output data from the multiplexer; wherein the multiplexer is not a static circuit.

Abstract: A speech coding apparatus and method measures the values of at least first and second different features of an utterance during each of a series of successive time intervals. For each time interval, a feature vector signal has a first component value equal to a first weighted combination of the values of only one feature of the utterance for at least two time intervals. The feature vector signal has a second component value equal to a second weighted combination, different from the first weighted combination, of the values of only one feature of the utterance for at least two time intervals. The resulting feature vector signals for a series of successive time intervals form a coded representation of the utterance. In one embodiment, a first weighted mixture signal has a value equal to a first weighted mixture of the values of the features of the utterance during a single time interval.

Abstract: The invention is a high density cross point folded bitline trench DRAM cell with a cell area of only 4 lithographic squares. The access device (transfer device) is vertically disposed on the side of a trench. In a preferred embodiment, poly spacer wordlines are used. The width of the wordlines can be increased, without increasing the cell area, by increasing the depth of the shallow trench. This will result in faster cell access due to the lower RC time constant of the wordline. The diffusion contact to the storage node, as well as the access device, is placed on one side of the trench to minimize the interaction between adjacent nodes, especially with scaling. The cell has a simple topography, and uses only one level of bitline wiring.