Abstract: A system for writing data to a disk array includes a cache memory coupled to the disk array for storing data indicative of locations on the disk array and parity blocks associated with parity groups including the locations. Each of the parity blocks includes an identifier indicative of locations within a particular parity group which are protected by the parity data. Write logic reads the identifier from the parity block, and based thereon, determines whether a disk location is not protected by the parity data. The write logic also writes to the location and updates the parity data and the identifier associated with the parity block to include the location of the data block to indicate that the location is protected.

Abstract: A digital dynamic circuit is presented which effectively extends the percentage of each clock cycle available for logical operations. The circuit uses a two-phase overlapping clocking design which results in the circuit (1) having only a single latch delay, (2) being insensitive to mid-cycle clock jitter, and (3) being insensitive to the discrete nature of gate delays. Thus, the circuit can better utilize the time available to perform logic.

Abstract: Analysis of a word input from a speech input device 1 for its features is made by a feature extractor 4 to obtain a feature vector sequence corresponding to said word, or to obtain a label sequence by applying a further transformation in a labeler 8. Fenonic hidden Markov models for speech transformation candidates are combined with N-gram probabilities (where N is all integer greater than or equal to 2) to produce models of words. The recognizer determines the probability that the speech model composed for each candidate word would output the label sequence or feature vector sequence input as speech, and outputs the candidate word corresponding to the speech model having the highest probability to a display 19.

Abstract: Benes networks are very effective in providing inter-processor communication in SIMD parallel machines, provided the communication patterns are compile-time determinable. These networks are ill suited when communication patterns are dynamically varying because of the long set up time requirements. The present invention is a method for handling dynamically varying communication patterns efficiently by operating the Benes network in a time division multiplexed manner, wherein during a given transmission period, the middle stage switches of the Benes network are configured as a portion of the middle stage switches of a Clos network configured to route all signals in a single period.

Abstract: A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.

Abstract: A method for making high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: A speech recognizer that selects a command model for a current sound if the best match score for the current sound exceeds its corresponding threshold score. The threshold score is assigned a confidence score based on the best match score and recognition threshold of a prior sound.

Abstract: A storage capacitor having high dielectric constant materials and a method for forming same are described. The method solves the problems associated with fabrication of planar capacitors for DRAM chips constructed from inorganic oxides with perovskite structure. These materials are not readily etched by conventional ion etching techniques. These materials also react with silicon and silicon dioxide and the disclosed process avoids these interactions.

Abstract: A programmable on-focal plane signal processor having analog to digital conversion, nonuniformity correction, gamma spike compensation all digitally performed on a single silicon substrate inside a dewar. The architecture supports time delay integration and spatial filtering to increase the signal to noise ratio of the focal plane array data. The processor has programmable coefficients which may be changed while the system is operating or eliminated. The architecture provides increased signal noise ratio for infrared data and decreases the output data bandwidth from the infrared focal plane array by two orders of magnitude.

Abstract: The invention concerns a computer system for speech recognition with a word table and a triphone table in its memory. In response to a new word not contained in the word table and which is encountered by the computer system during recognition of an unknown spoken text, the fenemic baseform of this new word may be synthetically produced with the aid of a triphone table. For this purpose, the new word is decomposed into triphones, and the fenemic sequences associated with the individual triphones are read from the triphone table. The fenemic sequences are concatenated according to the phonetic baseform of the new word such that the fenemic baseform of the new word is obtained.

Abstract: A novel bias generator circuit for a voltage controlled oscillator is described. The bias generator allows the VCO frequency to be made essentially independent of the supply voltage and temperature.

Abstract: An online handwritten character recognition system which performs the narrowing of candidates for handwritten character recognition quickly and very accurately by simple processing of a small amount of operations. A predetermined characteristic amount is extracted for each stroke, a characteristic amount word is created having a binary value of 1 only in one or more bit positions corresponding to selected values of the characteristic amount, an AND operation is performed bit-by-bit between the reference word of the corresponding stroke of the character of interest, and it is determined if all the bits of the results of the AND operation are zero. If the number of binary values of the results of the zero-determining operation for all the strokes of the character of interest exceeds a threshold, it is judged to be a candidate.

Abstract: A high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: A fully-symmetric high-speed CMOS frequency synthesizer which exhibits minimum dead-zone effects is disclosed. A fully-symmetric phase-frequency detector and a fully differential charge-pump filter combined with a voltage-controlled oscillator are key elements of the invention described.

Abstract: A storage capacitor having high dielectric constant materials and a method for forming same are described. The method solves the problems associated with fabrication of planar capacitors for DRAM chips constructed from inorganic oxides with perovskite structure. These materials are not readily etched by conventional ion etching techniques. These materials also react with silicon and silicon dioxide and the disclosed process avoids these interactions.

Abstract: A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+.DELTA.pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0<.DELTA.p<1. The amount of the delay is dependent on the value of a source delay select signal. A local data receiver receives data signals from a local receiver delay circuit. The amount of delay of the local receiver delay circuit is also selectable.

Abstract: A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver.

Abstract: A line space baseline adjuster in a handwriting recognition system achieves improved recognition accuracy by normalizing the Cartesian coordinates of the writings captured by a digitizer to coincide with prototype character space. The normalization techniques include weighted average estimation, prototype extraction estimation, extreme point clustering estimation and a combination of prototype extraction estimation and extreme point clustering estimation.

Abstract: A cache memory having rows of memory cells, each row having at least first and second blocks of memory cells. Each memory cell stores a data signal, has at least one word line input, and at least one bit line input/output. A word line connects the word line inputs of at least first, second, third, and fourth memory cells in a row of the cache memory. The first and third memory cells are contained in the first block, while the second and fourth memory cells are contained in the second block. First and second sense amplifiers or write drivers are provided for reading data from or writing data to memory cells. First and second switches having control inputs connect the bit line inputs/outputs of the first and second memory cells, respectively, to the first sense amplifier/write driver. Third and fourth switches having control inputs switchably connect the bit line inputs/outputs of the third and fourth memory cells, respectively, to the second sense amplifier/write driver.

Abstract: A natural language (NL) analyzing system is provided with the capability to analyze NL expressions and to resolve ambiguities and present them to the user for verification of correct interpretation. A conceptual model of the system, relevant to the application in which the invention is implemented, is created (customizing the system) by the user, and is stored as a conceptual schema. The schema is built of logical facts representing entities (concepts) and relationships between entities, forming a description of the universe of discourse or object system in question. The entities of the schema have at least one external connection, namely to natural language terms in a vocabulary. The schema itself is completely language independent, though the components of it may have "names" expressed in a natural language such as English. There may be a second connection to the entities, namely where the system is used in a query system for relational data bases.