Abstract: For use by a particular node within a digital data communications network having a plurality of counter-synchronized nodes including the particular node, called the central service node (CSN), and at least one remote node, all nodes being clocked at a common frequency, each node being synchronized by its own nodal time counter and connected to at least one other node by at least one transmission segment that completes a transmission path from the CSN, method and apparatus for: (a) establishing any value of virtual transmission delay (vtd) at individual transmission segments; (b) non-destructively determining the existing vtd at individual transmission segments; and (c) establishing basal distributions of vtd throughout the network and determining the elements thereof, (a), (b), and (c) being achieved without the central service node knowing real transmission delay (rtd) and inter-nodal asynchrony anywhere within the network and without requiring the active participation of any remote node.

Abstract: A data processing apparatus for simultaneously reading out groups of two or more contiguous, variable length instructions from memory, and for decoding the group of variable length instructions in parallel. The data processing apparatus has a memory containing at least first, second, and third contiguous instructions, and at least first, second, and third read ports for receiving starting addresses and for reading out the instructions from the memory. A next instruction pointer supplies the starting address of the first instruction to the first read port, receives the first instruction, decodes the length of the first instruction, determines the starting address of the second instruction, supplies the starting address of the second instruction to the first read port, receives the second instruction, decodes the length of the second instruction, and determines the starting address of the third instruction. All of these operations are performed in one cycle time.

Abstract: A communication network having a service processor, a plurality of terminal nodes, and a network of switch nodes for switchably connecting the service processor to each terminal node by way of one or more connection paths. Each switch node in the communication network is connected to the service processor either directly or through one or more other switch nodes. Each terminal node of the communication network is connected to a switch node. Each switch node and each terminal node has a device identification. At least two nodes have the same device identification. Each target node having the same device identification as another node can preferably be connected to the service processor by way of at least one connection path which does not include any other node having the same device identification as the target node. All switch nodes having the same minimum connection path length may, for example, have the same device identification.

Abstract: A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance. During memory address generation operations, an arithmetic-logic unit (ALU) generates memory addresses from data in a general purpose register (GPR). Then, the memory addresses are written back to the GPR and a memory address register (MAR). During memory access operations, the MAR is accessed for the memory addresses to access a memory. Two approaches are provided. In a first approach, use of the MAR during the memory access operations is explicit. In a second approach, use of the MAR during the memory access operations is transparent. According to the second approach, a controller is provided to validate the MAR during the memory access operations.

Abstract: A method of sending an electronic message from a source station through a network of switches and links to a destination station. An electronic message is sequentially sent to each of a series of switches. Each switch reads a route signal in the message and sends the message to a switch or a station having an input port connected to an output port identified by the route signal. The route signals are generated by storing a weight for each switch link in the network. Candidate paths through the switch network starting at the source station and ending at initial candidate destinations are identified. Each initial candidate destination has an input port directly connected to an output port of a switch having an input port directly connected to the source station. If one or more candidate destinations are the destination station, a candidate path ending at the destination station is selected, and a series of route signals corresponding to the selected candidate path is generated.

Abstract: A signal processing card packaged on a bus of a personal computer has a bus master which is used to access the main memory of the personal computer. A large table of probability values required for speech recognition is held in the main memory. When a label to be processed is generated, only the necessary part of the table is read from the main memory to the memory on the signal processing card by direct memory access transfer to perform speech recognition processing.

Abstract: Method and apparatus for automatic recognition of handwritten text based on a suitable representation of handwriting in one or several feature vector spaces(s), Gaussian modeling in each space, and mixture decoding to take into account the contribution of all relevant prototypes in all spaces. The feature vector space(s) is selected to encompass both a local and a global description of each appropriate point on a pen trajectory. Windowing is performed to capture broad trends in the handwriting, after which a linear transformation is applied to suitably eliminate redundancy. The resulting feature vector space(s) is called chirographic space(s). Gaussian modeling is performed to isolate adequate chirographic prototype distributions in each space, and the mixture coefficients weighting these distributions are trained using a maximum likelihood framework. Decoding can be performed simply and effectively by accumulating the contribution of all relevant prototype distributions.

Abstract: A method of displaying a high resolution multicolor image on a lower resolution display. The image comprises a plurality of image pixels containing at least first and second image subpixels having first and second colors. The image is displayed on a display having display pixels comprising at least first and second spatially offset display subpixels capable of displaying the first and second colors, respectively. In the method, the first display subpixel is displayed with an intensity which is a function of the intensities of at least two first image subpixels having positions extending over a first region having an area greater than the area of the first display subpixel. The first region is approximately centered on the position of the first display subpixel. A second display subpixel is displayed with an intensity which is a function of the intensities of at least two second image subpixels having positions extending over a second region having an area greater than the area of the second display subpixel.