Abstract: A disk operating system converts virtual storage space locations of one or more processes into real disk or core memory storage space locations of a computer system. Real and virtual storage space are divided into equal sized pages. Real storage pages are grouped into variable sized segments and a separate segment page table is provided for each real storage segment, each entry therein characterizing the nature and location of a page. A separate process map list is provided for each process, each entry therein mapping an area of contiguous virtual storage pages onto a segment page table. Before a process executes a program, the operating system uses the associated process map list, along with the segment page tables mapped by the list, to create a process page table which directly maps virtual storage pages of a process into real storage pages.

Abstract: A frame buffer memory has a random access memory (RAM) for storing pixel data words, each word containing pixel data corresponding to a separate set of a plurality pixels along a horizontal raster line of a screen display. Each word is separately addressed.The RAM is organized into tiles, with each tile comprising an array of pixel data word rows and columns corresponding to a separate rectangular subset of horizontally and vertically contiguous display pixels. The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel word row within each tile is addressed, while and a second subset of the column address determines which pixel word column within each tile is addressed. All other bits of the row and column addresses determine which tile is addressed.

Abstract: A dual channel time domain reflectometer includes a pair of input lines connected at respective nodes to a reference flat current pulse generator and a traveling wave sampling gate, respectively. The sampling gates are actuated by a balanced strobe generator which includes a waveguide coupler for coupling a high amplitude fast rise time pulse to each of the gates simultaneously. Pulses of requisite amplitude and shape are generated by a circuit responsive to a strobe trigger input which drives a step recovery diode.

Abstract: A method and apparatus are disclosed which provide for the generation of a trigger signal responsive to the detection of a plurality of selected sequential events in a single monitored signal. A plurality of trigger detect devices operate independently to monitor a signal for the occurrence of selected trigger criteria, and produce indications thereof having selected durations. The duration of the indications function to provide continuous indications of the occurrence of the selected trigger conditions over the periods thereof. In one embodiment, a state machine delays each of the indications by an amount of time approximately equal to the time between the respective events and a final event in the sequence, thereafter combining the indications according to preselected logical operations. As a result of the delays, the indications from the trigger detect devices are combined at approximately the same time.

Abstract: An angle modulated periodic waveform is synthesized by generating three digital number sequences. In a first number sequence, one number thereof is generated on each occurrence of a periodic clock signal and has a magnitude which is a selected first periodic function of the number of prior occurring clock signals. In a second number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected second function of prior occurring numbers of the first number sequence and an applied constant carrier waveform frequency parameter. Each number of the second number sequence is added as it is generated to a stored second address number. In the third number sequence, one number thereof is generated on each occurrence of the clock signal and has a magnitude which is a selected third periodic function of the stored second address number.

Abstract: A measurement is carried out on a medium that propagates energy in a selected form by applying energy in the selected form to the medium, the power varying as a function of time in accordance with the elements of two Golay complementary sequences where one kind of element is represented by zero power and the other kind of element is represented by a predetermined non-zero power level and the successive elements of each sequence are applied at uniform intervals. Energy emitted from the medium in the selected form is received, and the variation as a function of time of the power emitted is correlated with the variation as a function of time of the power that was applied. Preferably, the level at which power is applied is varied both directly, in accordance with the elements of the two Golay complementary sequences, and in a derivative fashion, in accordance with the logical complements of the two Golay complementary sequences.

Abstract: A visible representation of a colored image is created on a print-receiving area by resolving the colored image into p raster lines and resolving each raster line into q pixels, and creating a succession of sequences of digital words such that each word is associated with a pixel of the image and has one of n possible values, representing the color of the pixel. Consecutive words in each sequence of digital words are associated with adjacent pixels in a raster line of the image and consecutive sequences in the succession of sequences are associated with adjacent raster lines. First, for each of the n possible values of each digital word, a measure of the number of words that have that value is determined. Second, a set of the n possible values is selected, such that the number yielded in the first step for each value is not zero. Third, a subset of the selected set is identified such that pixels having the colors represented by the values in the subset do not appear adjacent each other in the image.

Abstract: A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are identically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appropriately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselected rules during a memory write operation prior to being written into memory.

Abstract: An end portion of an elongate member of generally cylindrical form, such as an optical fiber, is placed in a predetermined position utilizing a substrate having a surface that is defined by a generatrix that is a straight line, e.g. a flat surface. A foil of flexible material is secured to the surface of the substrate and defines with the substrate a generally straight, elongate passageway that is parallel to the generatrix of the surface and has a first portion of substantially uniform cross-section adapted to receive an end of the elongate member in closely fitting relationship and also has a second portion that tapers towards the first portion. The end portion of the elongate member is inserted into the first portion of the passageway by way of the second portion thereof.

Abstract: A reverse current transmitted through an initially forward biased step-recovery diode causes the step-recovery diode to switch from the forward biased state to a reverse biased state, thereby developing an abruptly rising reverse bias voltage across the step-recovery diode. The abruptly rising reverse bias voltage is applied across a series combination of a capacitor and a laser diode, connected in parallel with the step-recovery diode to force a short, abrupt forward current pulse through the laser diode, thereby causing the laser diode to emit a short optical pulse.

Abstract: An electro-optic sampler comprises a body of semiconductor material that can be energized to emit polarized light, a photodetector device for generating an electrical output signal representative of the intensity with which light polarized in a predetermined manner is incident on the photodetector device, and a body of electro-optic material defining an optical waveguide for transmitting light from the source of polarized light to the photodetector. First and second electrodes are provided for establishing an electrical field within the body of electro-optic material. The body of electro-optic material has a spherical index ellipsoid when the first and second electrodes are at the same potential and otherwise has a non-spherical index ellipsoid.

Abstract: A graphics display terminal performs a pan operation with respect to a view motion center to effectuate spherical panning, thereby providing perspective and non-perspective views. Three dimensional instructions stored in terminal memory are re-transformed in accordance with a panned direction. Also a zoom feature is provided so that displayed images may be magnified as desired.

Abstract: A testing method and apparatus employs electron beam writing and reading of conductive paths in a circuit device rather than physical probing of conductive elements. Portions of the circuit device, e.g., conductive paths, are bistably stored at a given potential and then the device is read by a reading beam to determine if proper connections exist. Read out is at comparatively high levels represented by the difference between bistable voltage values. Once a portion of the device has been tested, it may remain in stored condition such that additional cross checking or repetition of testing is rendered unnecessary.

Abstract: A time stamp circuit comprises a plurality of counter programmable logic arrays for providing a Gray code count. Each count provided by the counters is associated as a time value with a specified event to be stored in memory. The count is generated automatically over a range of progressively slower frequencies provided by frequency dividing circuitry connected to an oscillator. The circuit has two modes of operation, a cumulative mode and a delta mode. In the cumulative mode, the count begins with the first occurrence of a specified event and ends when acquisition is halted. In the delta mode, a control programmable logic array automatically resets the Gray code count and thereby the clock frequency to its highest frequency each time a specified event is stored. The resolution, or time between counts, therefore is the same to begin between each pair of events.

Abstract: Color dither patterns are read into a pixel bit map memory used to form a color display by means of concurrently addressing a pattern memory storing the dither patterns. Lower order address bits repeatedly access a preselected portion of the pattern memory to supply the dither pattern which is written as data into the pixel bit map memory.

Abstract: A method of testing an electronic circuit of the kind having an input port for receiving input vectors, an output port for providing output vectors, and a serial scan port for providing at least one serial scan vector reflecting the status of predetermined elements within the circuit, is performed by applying a sequence of test vectors to the input port as a plurality of sub-sequences each including at least one test vector. The serial scan vector is examined after each sub-sequence, and a determination is made as to whether a part of the serial scan vector indicates the presence of a defect in the circuit. In the event that part of the serial scan vector indicates the presence of a defect in the circuit, the corresponding part of a succeeding serial scan vector is prevented from indicating the presence of a defect.

Abstract: A system for assembling electronic work stations including multiple electronic units. The electronic units are provided as subassemblies, premounted into specially formed trays. Special slide engaging male and female mounting components have one of the components formed into the chassis and the other component formed into the tray. The subassemblies are simply slid into place and various locking means are automatically engaged as the subassemblies are forced into their "home" position. The assembly time is greatly reduced resulting in substantial savings.

Abstract: A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.

Abstract: A digital-to-analog converter comprises a current source for supplying a current of predetermined magnitude to a circuit node, and a switch connected to the circuit node, and defining a first current path leading to a reference potential terminal and a second current path leading to an output terminal. The switch has an input terminal, at which it receives a first digital signal of one binary digit for conversion to analog form, and also has a reference terminal, and has a first condition, when the voltage at the reference terminal is higher than that at the input terminal, in which the current supplied to the circuit node is delivered to the output terminal, and a second condition, when the voltage at the reference terminal is lower than that at the input terminal, in which the current is delivered to the reference potential terminal.

Abstract: A load-dependent current limiter for the power supply of a multi-module electronic system has a programming resistor in each module connected between the power supply voltage and a reference bus. The current through each programming resistor is proportional to the current requirements of the module. The voltage of the reference bus, which is proportional to the total current through all the programming resistors, is compared to the voltage developed across a sensing resistor by the total power supply current. When the sense voltage exceeds the reference voltage, indicative of tapping excess power, a signal is sent from the comparator to shutdown the power supply.