Patents Represented by Attorney Robinson Intellectual Property Law Office, P.C.
  • Patent number: 8247308
    Abstract: It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa, Motomu Kurata, Atsushi Hikosaka, Taiga Muraoka, Hitoshi Nakayama
  • Patent number: 8247315
    Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Furuno, Tetsuo Sugiyama, Taichi Nozawa, Mitsuhiro Ichijo, Ryota Tajima, Shunpei Yamazaki
  • Patent number: 8247250
    Abstract: An object is to uniformly align liquid crystal molecules without requiring a step of forming an alignment film. A material for forming a self-assembled monolayer is dispersed in a liquid crystal material, and the mixture is interposed between a pair of substrates by a liquid crystal injection method or a liquid crystal dropping method. A silane coupling agent (the material for forming a self-assembled monolayer) injected or dropped with the liquid crystal material adsorbs to a substrate interface (or a surface of an electrode formed over a substrate) after the injection or dropping, thereby forming a self-assembled monolayer. This self-assembled monolayer serves as an alignment film, and enables long axes of liquid crystal molecules to be approximately perpendicular to a substrate and the liquid crystal molecules to be uniformly aligned.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Takeshi Nishi, Akio Yamashita
  • Patent number: 8247812
    Abstract: An object is to suppress deterioration in electric characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer, an impurity semiconductor layer is provided over the silicon layer, and a source electrode layer and a drain electrode layer are provided to be electrically connected to the impurity semiconductor layer.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Patent number: 8247813
    Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 8242496
    Abstract: An object is to increase an aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over one substrate. The driver circuit portion includes a channel-etched thin film transistor for a driver circuit, in which a source electrode and a drain electrode are formed using metal and a channel layer is formed of an oxide semiconductor, and a driver circuit wiring formed using metal. The display portion includes a channel protection thin film transistor for a pixel, in which a source electrode layer and a drain electrode layer are formed using an oxide conductor and a semiconductor layer is formed of an oxide semiconductor, and a display portion wiring formed using an oxide conductor.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara, Ikuko Kawamata
  • Patent number: 8242494
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka, Shunichi Ito, Miyuki Hosoba
  • Patent number: 8240577
    Abstract: An object of the present invention is to achieve a wireless chip with high reliability, a small chip area, and low power consumption, where voltage that is generated inside is prevented from excessively increasing also in a strong magnetic field such as in the case of approaching an antenna. A resonant circuit including a MOS capacitor element that has a predetermined threshold voltage is used to achieve a wireless chip. This allows a parameter of the resonant circuit to be prevented from changing in the case where the voltage amplitude exceeds a predetermined value in a strong magnetic field so that the wireless chip can be kept far away from the resonant condition. Accordingly, generation of excessive voltage is allowed to be prevented without the use of a limiter circuit or a constant voltage generation circuit.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 8242585
    Abstract: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Hiroki Adachi, Junya Maruyama, Naoto Kusumoto, Yuusuke Sugawara, Tomoyuki Aoki, Eiji Sugiyama, Hironobu Takahashi
  • Patent number: 8242002
    Abstract: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10?7/° C. and less than or equal to 38×10?7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser beam having a width of less than or equal to 100 ?m, a ratio of width to length of 1:500 or more, and a full width at half maximum of the laser beam profile of less than or equal to 50 ?m, so that a crystalline semiconductor film is formed. As the layer including the semiconductor film formed over the glass substrate, a layer whose total stress after heating is ?500 N/m to +50 N/m, inclusive is formed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Yasuhiro Jinbo
  • Patent number: 8242903
    Abstract: A wireless sensor device capable of constant operation without replacement of batteries. The wireless sensor device is equipped with a rechargeable battery and the battery is recharged wirelessly. Radio waves received at an antenna circuit are converted into electrical energy and stored in the battery. A sensor circuit operates with the electrical energy stored in the battery, and acquires information. Then, a signal containing the information acquired is converted into radio waves at the antenna circuit, whereby the information can be read out wirelessly.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 8242592
    Abstract: An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by stacking a conductive film 11, a resin film 13, an integrated circuit 12, and a resin film 14 are rolled so that the resin film 14 is outside. Then, the laminated body is integrated in a roll form by softening the resin films 13, 14 by applying heat. By slicing the rolled laminated body along with the direction in which the rolled conductive film 31 appears in the cross section, an IC chip with antenna formed by the rolled conductive film 11 is formed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Kusumoto, Takuya Tsurume
  • Patent number: 8243863
    Abstract: To provide a semiconductor device which can transmit/receive data to/from a reader/writer without interruption of operation by the reader/writer or the like. A semiconductor device capable of wireless communication includes an antenna circuit, a first demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% to 100%, both inclusive, a second demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% and 100%, both inclusive and from 10% and 30%, both inclusive and a logic circuit which selects one of a demodulation signal from the first circuit and a demodulation signal from the second circuit. When the antenna circuit receives an electromagnetic wave, the logic circuit selects the demodulation signal from the second circuit, and when the antenna circuit transmits an electromagnetic wave, the logic circuit selects the demodulation signal from the first circuit.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidetomo Kobayashi
  • Patent number: 8242486
    Abstract: An object is to provide technology for manufacturing a higher-reliability memory device and a semiconductor device that is equipped with the memory device at low cost. A semiconductor device of the present invention has a first conductive layer, a first insulating layer that is provided to be in contact with a side end portion of the first conductive layer, a second insulating layer that is provided over the first conductive layer and the first insulating layer, and a second conductive layer that is provided over the second insulating layer. The second insulating layer is formed of an insulating material, and wettability against a fluidized substance when the insulating material is fluidized, is higher for the first insulating layer than the first conductive layer.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Gen Fujii
  • Patent number: 8242508
    Abstract: A semiconductor device includes a thin film transistor. The thin film transistor includes a semiconductor film over a substrate, in which the semiconductor film includes a pair of first regions, a pair of second regions interposed between the pair of first regions, and a channel formation region interposed between the pair of second regions. A concentration of an impurity in the pair of second regions is smaller than a concentration of the impurity in the pair of first regions. The thin film transistor includes an insulating film, in which a portion of the insulating film is provided over the semiconductor film. The thin film transistor includes a conductive film over the portion, and the conductive film includes a taper shape.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hamada, Yasuyuki Arai
  • Patent number: 8243873
    Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hiroyuki Miyake
  • Patent number: 8242971
    Abstract: In a multi-window display device, the following has been merely performed: before data for plural screens is inputted to a display, video signals themselves are subjected to signal processing, and the processed video signals are inputted to the display, whereby display is performed. Therefore, a circuit for performing signal processing, for example, an IC has a complicated structure since video signals for plural screens are stored in a memory. There is provided a pixel structure in which: signal lines for plural screens are arranged; and one of the signal lines is selected to supply a video signal to a display element. For example, in the case of performing display of two screens, there is provided a pixel structure in which: two signal lines, which are inputted with respective video signals for a first screen and a second screen, are arranged; and one of the signal lines is selected to supply a video signal from the selected signal line to a display element.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Shunpei Yamazaki
  • Patent number: 8241949
    Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode over a substrate having an insulating surface; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film over the gate insulating film; irradiating the oxide semiconductor film with an electromagnetic wave such as a microwave or a high frequency; forming a source electrode and a drain electrode over the oxide semiconductor film irradiated with the electromagnetic wave; and forming an oxide insulating film, which is in contact with part of the oxide semiconductor film, over the gate insulating film, the oxide semiconductor film, the source electrode, and the drain electrode.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akiharu Miyanaga
  • Patent number: 8242988
    Abstract: A light emitting device comprising a light emitting element and a first transistor and a second transistor controlling current to be supplied to the light emitting element in a pixel; the first transistor is normally-on; the second transistor is normally-off; a channel length of the first transistor is longer than a channel width thereof; a channel length of the second transistor is equal to or shorter than a channel length thereof; gate electrodes of the first transistor and the second transistor are connected to each other; the first transistor and the second transistor have the same polarity; and the light emitting element, the first transistor and the second transistor are all connected in series.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Mitsuaki Osame, Takashi Hamada, Tamae Takano, Yu Yamazaki, Aya Anzai
  • Patent number: 8241997
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki