Patents Represented by Attorney Robinson Intellectual Property Law Office, P.C.
  • Patent number: 8278974
    Abstract: A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Yoshiaki Ito
  • Patent number: 8278187
    Abstract: Disclosed is a method for reprocessing a semiconductor substrate which is by-produced in manufacturing a silicon-on-insulator substrate. The method includes: forming an embrittlement layer in a single crystal semiconductor substrate; bonding the single crystal semiconductor substrate with a base substrate having an insulating surface; and separating the single crystal semiconductor substrate along the embrittlement layer to give a silicon-on-insulator substrate and a semiconductor substrate to be reprocessed. The above steps provide, in the peripheral portion on the semiconductor substrate, a projection comprising the embrittlement layer and a single crystal semiconductor layer over the embrittlement layer. The method is characterized by an etching step to selectively remove the projection without etching a portion where the projection is absent, which allows the semiconductor substrate to be reused for the production of another silicon-on-insulator substrate.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuya Hanaoka
  • Patent number: 8278713
    Abstract: To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunio Hosoya, Saishi Fujikawa, Takahiro Kasahara
  • Patent number: 8278444
    Abstract: An organometallic complex according to the present invention comprises a structure represented by the following general formula (1). In the formula, R1 to R5 are any one selected from the group consisting of hydrogen, a halogen element, an acyl group, an alkyl group, an alkoxy group, an aryl group, a cyano group, and a heterocyclic group, Ar is an aryl group having an electron-withdrawing group or a heterocyclic group having electron-drawing group, and M is an element of Group 9 or an element of Group 10.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideko Inoue, Satoshi Seo, Satoko Shitagaki, Hiroko Abe
  • Patent number: 8278162
    Abstract: A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Daisuke Kawae
  • Patent number: 8279085
    Abstract: An information distribution system comprises a roadside apparatus, a center apparatus, and a vehicle-mounted device. The center apparatus transmits to a predetermined area through the roadside apparatus first distribution information including a predetermined division number for identifying a road where the roadside apparatus are installed or second distribution information including speech information, a division number, and execution condition information for executing the speech information depending on the division number included in the first distribution information and that included in the second one.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Kenwood
    Inventor: Satoru Sekiguchi
  • Patent number: 8278657
    Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Patent number: 8278195
    Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
  • Patent number: 8273583
    Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Yoshimi Adachi, Noriko Shibata
  • Patent number: 8273637
    Abstract: Suppression of generation of a stripe pattern (unevenness) when an SOI substrate is manufactured by a glass substrate and a single crystal semiconductor substrate bonded to each other. A single crystal semiconductor substrate is irradiated with ions so that a fragile region is formed in the single crystal semiconductor substrate; a depression or a projection is formed in a region of a surface of an insulating layer provided on the single crystal semiconductor substrate, the region corresponding to the periphery of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate; thermal treatment is performed thereon to separate the single crystal semiconductor substrate at the fragile region, so that a single crystal semiconductor layer is formed over the base substrate; and the single crystal semiconductor layer in the region corresponding to the periphery is removed.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kenichiro Makino
  • Patent number: 8274079
    Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8273613
    Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Toshimitsu Konuma, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi
  • Patent number: 8273611
    Abstract: A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an insulating layer on the single crystal semiconductor substrate to which the plasma treatment is performed; bonding the single crystal semiconductor substrate to the substrate having the insulating surface with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate using the ion doped layer as a separation surface. As a result, a semiconductor substrate in which a defect in an interface between the single crystal semiconductor layer and the insulating layer is reduced can be provided.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Kazutaka Kuriki
  • Patent number: 8274814
    Abstract: A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Hajime Tokunaga, Toshihiko Saito
  • Patent number: 8273898
    Abstract: Provided is a bipolar substance having high excitation energy, in particular, high triplet-excitation energy. An oxadiazole derivative represented by General Formula (G1) below is provided In the formula, Ar represents a substituted or unsubstituted aryl group having 6 to 10 carbon atoms in a ring. R1 represents an alkyl group having 1 to 4 carbon atoms or a substituted or unsubstituted aryl group having 6 to 10 carbon atoms in a ring. R2 represents hydrogen, an alkyl group having 1 to 4 carbon atoms, or a substituted or unsubstituted aryl group having 6 to 10 carbon atoms in a ring.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Nomura, Sachiko Kawakami, Nobuharu Ohsawa, Satoshi Seo
  • Patent number: 8274628
    Abstract: In the present invention, it is an object to improve display quality by improving response speed of a liquid crystal element in a liquid crystal display device, in particular, response speed in the case of falling. In the present invention, it is characterized that a liquid crystal layer is divided into plural regions (domains) substantially by mixing a chemical compound including a liquid crystal skeleton in a liquid crystal layer having existing liquid crystal molecules as a technique to improve response speed of a liquid crystal element in a liquid crystal display device for solving the above problem.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Nishi, Tetsuji Ishitani, Daisuke Kubota
  • Patent number: 8268702
    Abstract: It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 18, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Mai Akiba
  • Patent number: 8268701
    Abstract: Instead of forming a semiconductor film by bonding a bond substrate (semiconductor substrate) to a base substrate (supporting substrate) and then separating or cleaving the bond substrate, a bond substrate is separated or cleaved at a plurality of positions to form a plurality of first semiconductor films (mother islands), and then the plurality of first semiconductor films are bonded to a base substrate. Subsequently, the plurality of first semiconductor films each are partially etched, whereby one or more second semiconductor films (islands) are formed using one of the first semiconductor films and a semiconductor element is manufactured using the second semiconductor films. The plurality of first semiconductor films are bonded to the base substrate based on a layout of the second semiconductor films so as to cover at least a region in which the second semiconductor films of the semiconductor element are to be formed.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 18, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8269225
    Abstract: An object of the invention is to provide a lighting device which can suppress luminance nonuniformity in a light emitting region when the lighting device has large area. A layer including a light emitting material is formed between a first electrode and a second electrode, and a third electrode is formed to connect to the first electrode through an opening formed in the second electrode and the layer including a light emitting material. An effect of voltage drop due to relatively high resistivity of the first electrode can be reduced by electrically connecting the third electrode to the first electrode through the opening.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 18, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuyuki Arai
  • Patent number: 8263926
    Abstract: It is an object to provide a photoelectric conversion device which detects light ranging from weak light to strong light. The present invention relates to a photoelectric conversion device having a photodiode having a photoelectric conversion layer, an amplifier circuit including a thin film transistor and a bias switching means, where a bias which is connected to the photodiode and the amplifier circuit is switched by the bias switching means when intensity of incident light exceeds predetermined intensity, and accordingly, light which is less than the predetermined intensity is detected by the photodiode and light which is more than the predetermined intensity is detected by the thin film transistor of the amplifier circuit. By the present invention, light ranging from weak light to strong light can be detected.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: September 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Atsushi Hirose, Kazuo Nishi, Yuusuke Sugawara