Patents Represented by Attorney Robinson Intellectual Property Law Office, P.C.
  • Patent number: 8243233
    Abstract: A liquid crystal device comprising: a pair of substrates having an electrode arrangement thereon; an orientation control means provided on at least one of said substrates; and a ferroelectric or antiferroelectric liquid crystal layer interposed between said substrates, said liquid crystal layer being uniaxially oriented by virtue of said orientation control means, wherein means for suppressing an orientation control effect of said orientation control means with respect to said liquid crystal layer is provided between said liquid crystal layer and said orientation control means.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Takeshi Nishi, Michio Shimizu, Harumi Mori, Kouji Moriya, Satoshi Murakami
  • Patent number: 8243220
    Abstract: It is an object to provide a highly reliable display device. It is a feature an IC is over a substrate and a material layer having the same height is thereover. An IC is provided on one side of the substrate, and a material layer having the same height as the IC is provided on at least another side. Further, an IC is provided on one side of the substrate, and material layers having the same height as the IC are provided on the other sides. Further, an IC is provided on one side of the substrate, and a material layer having the same height as the IC is provided at a corner of the substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8237167
    Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8236630
    Abstract: An embrittlement layer is formed in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions, and an insulating layer is formed over the main surface of the single crystal semiconductor substrate. The insulating layer and a substrate having an insulating surface are bonded, and the single crystal semiconductor substrate is separated along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface. Then, an n-channel transistor and a p-channel transistor are formed so as to each have a <110> axis of the single crystal semiconductor layer in a channel length direction.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8238152
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Yoshinobu Asami, Tamae Takano, Masayuki Sakakura, Ryoji Nomura, Shunpei Yamazaki
  • Patent number: 8237569
    Abstract: When a product attached with an ID tag is placed inside a package body, there is a risk that communication with an ID tag using a reader/writer is blocked. Then, it is difficult to manage products in a distribution process of products, which leads to lose convenience of ID tags. One feature of the present invention is a product management system that includes a package body for packing a product attached with an ID tag, and a reader/writer. The ID tag includes a thin film integrated circuit portion and an antenna, the package body includes a resonance circuit portion having an antenna coil and a capacitor, and the resonance circuit portion can communicate with the reader/writer and the ID tag. Accordingly, the stability of communication between an ID tag attached to a product and an R/W can be secured, and management of products can be conducted simply and efficiently, even if a product is packed by a package body.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuyuki Arai, Mai Akiba, Yuko Tachimura, Yohei Kanno
  • Patent number: 8237176
    Abstract: The present invention provides a structure in which a pixel region 13 is surrounded by a first sealing material (having higher viscosity than a second sealing material) 16 including a spacer (filler, minute particles and/or the like) which maintains a gap between the two substrates, filled with a few drops of the transparent second sealing material 17a which is spread in the region; and sealed by using the first sealing material 16 and the second sealing material 17.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Yumiko Ohno
  • Patent number: 8237164
    Abstract: (OBJECT) The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. (MEANS FOR SOLVING THE PROBLEM) In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno, Masakazu Murakami, Toshiji Hamatani, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 8237248
    Abstract: An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiaki Oikawa, Hironobu Shoji, Yutaka Shionoiri, Kiyoshi Kato, Masataka Nakada
  • Patent number: 8236635
    Abstract: In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8236627
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Patent number: 8236629
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
  • Patent number: 8232598
    Abstract: To provide a display device which can realize high performance of a field-effect transistor which forms a pixel of the display device and which can achieve improvement in an aperture ratio of a pixel, which has been reduced due to increase in the number of field-effect transistors, and reduction in the area of the field-effect transistor which occupies the pixel, without depending on a microfabrication technique of the field-effect transistor, even when the number of field-effect transistors in the pixel is increased. A display device is provided with a plurality of pixels in which a plurality of field-effect transistors including a semiconductor layer which is separated from a semiconductor substrate and is bonded to a supporting substrate having an insulating surface are stacked with a planarization layer interposed therebetween.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Atsushi Miyaguchi
  • Patent number: 8232621
    Abstract: When letters are written with a ballpoint pen, pen pressure is greater than or equal to 10 MPa. The IC tag embedded in the paper base material is required to withstand such pen pressure. An integrated circuit including a functional circuit which transmits and receive, performs arithmetic of, and stores information is thinned, and also, when the integrated circuit and a structural body provided with an antenna or a wiring are attached, a second structural body formed of ceramics or the like is also attached to at the same time. When the second structural body formed of ceramics or the like is used, resistance to pressing pressure or bending stress applied externally can be realized. Further, a part of passive elements included in the integrated circuit can be transferred to the second structural body, which leads to reduction in area of the semiconductor device.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8232181
    Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with a second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Jun Koyama
  • Patent number: 8231424
    Abstract: A light-emitting element is provided which has a light-emitting layer between a first electrode and a second electrode, where the light-emitting layer has a first layer and a second layer; the first layer contains a first organic compound and a third organic compound; the second layer contains a second organic compound and the third organic compound; the first layer is provided to be in contact with the second layer on the first electrode side; the first organic compound is an organic compound with an electron transporting property; the second organic compound is an organic compound with a hole transporting property; the third organic compound has an electron trapping property; and light emission from the third organic compound can be obtained when voltage is applied to the first electrode and the second electrode so that the potential of the first electrode is higher than that of the second electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hideko Inoue, Satoshi Seo, Nobuharu Ohsawa
  • Patent number: 8232880
    Abstract: The present invention provides a battery as a power supply for supplying power in the RFID, and another antenna for charging the battery, in addition to an antenna which transmits and receives individual information to and from outside as a means for supplying power to the battery.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masato Ishii, Tomoaki Atsumi, Takeshi Osada, Takayuki Ikeda, Yoshiyuki Kurokawa, Yutaka Shionoiri
  • Patent number: 8232555
    Abstract: It is an object of the present invention to provide a device suitable for new usage by making use of a semiconductor device such as an RFID tag in terms of the capability to transmit and receive data without being contacted therewith, to decrease a burden on a user, and to improve convenience. A semiconductor device is provided to have an arithmetic processing circuit including a transistor, a conductive layer serving as an antenna, a detecting unit having a means for detecting physical quantity or chemical quantity, and a storage unit for storing data detected by the detecting unit, and to cover the arithmetic processing circuit, the conductive layer, the detecting unit, and the storage unit with a protective layer. In addition, diverse information can be monitored and controlled by providing such a semiconductor device for human beings, animals and plants, or the like without being contacted therewith.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yumiko Noda, Yasuyuki Arai, Yasuko Watanabe, Yoshitaka Moriya, Shunpei Yamazaki
  • Patent number: 8227886
    Abstract: An object is to reduce the breakage of appearance such as a crack, a split and a chip by external stress of a semiconductor device. Another object is that manufacturing yield of a thin semiconductor device increases. The semiconductor device includes a plurality of semiconductor integrated circuits mounted on the interposer. Each of the plurality of semiconductor integrated circuits includes a light transmitting substrate which have a step on the side surface and in which the width of one section of the light transmitting substrate is narrower than that of the other section of the light transmitting substrate when the light transmitting substrate is divided at a plane including the step, a semiconductor element layer including a photoelectric conversion element provided on one surface of the light transmitting substrate, and a chromatic color light transmitting resin layer which covers the other surface of the light transmitting substrate and a part of the side surface.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: July 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Takahashi, Yohei Monma, Daiki Yamada, Takahiro Iguchi, Kazuo Nishi
  • Patent number: 8227600
    Abstract: It is an object of the present invention to provide a substance capable of emitting phosphorescence. In addition, it is an object of the present invention to provide a light-emitting element that is excellent in chromaticity. One aspect of the present invention is an organometallic complex having a structure represented by a general formula (1). In the general formula (1), R1 to R4 are each any one of hydrogen, a halogen element, an acyl group, an alkyl group, an alkoxyl group, an aryl group, a cyano group, and a heterocyclic group. In addition, R5 to R13 are each any one of hydrogen, an acyl group, an alkyl group, an alkoxyl group, an aryl group, a heterocyclic group, and an electron-withdrawing group. An organometallic complex having such a structure can emit phosphorescence with higher emission intensity.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: July 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideko Inoue, Satoko Shitagaki, Satoshi Seo