Abstract: A method and system for estimating the worst case corrosion in a pipeline for which pipeline wall thickness measurements are limited to sampled ultrasonic or radiography (UT/RT) measurements. A data library contains distributions of in-line inspection (IL) measurements for other pipelines, calibrated to correspond to UT/RT measurements as needed. These ILI datasets are randomly sampled multiple times, to obtain multiple sample sets from each ILI dataset. Candidate statistical distributions are evaluated for each sample set to determine which of the candidate statistical distributions most accurately estimates the worst case corrosion measured by ILI. A discriminant function is then derived from sample statistics and pipeline descriptors associated with the sample sets, along with the best candidate statistical distribution for that sample set.

Abstract: A computer system and method of operating the same to optimize the operating conditions of a petroleum production field, in which a plurality of wells are arranged according to drill sites, and connected to one or more central processing facilities, is disclosed. In this disclosed embodiment, gas compression capacity is a significant constraint on the operation of the complex production field, and surface line hydraulic effects of well production are to be considered in the optimization. A genetic algorithm is used to generate, and iteratively evaluate solution vectors, which are combinations of field operating parameters such as incremental gas-oil ratio cutoff and formation gas-oil ratio cutoff values. The evaluation includes the operation of an adaptive network to determine production header pressures, followed by modification of well output estimates to account for changes in the production header pressure.

Abstract: A computer system (30) and method of operating the same to analyze well log data so as to distinguish fractures from drilling artifacts, such as caves, washouts, and breakouts, is disclosed. According to the disclosed system and method, a Stoneley wave well log obtained at a plurality of depths is analyzed at a low and a high frequency, to generate a low frequency reflection coefficient trace over depth and a high frequency reflection coefficient trace over depth. Comparison of these reflection coefficient traces with one another will indicate whether a reflecting feature includes a fracture (as indicated by good low frequency response) or a cave, washout, or other artifact (as indicated by good high frequency response), or both. The particular methods disclosed include the generation of the reflection coefficient traces through back-projection stacking of deconvolved impulse traces at both frequencies, and applying and evaluating an envelope function to the stacked traces.

Abstract: A circuit for operating a polyphase DC motor, such as the type having a plurality of "Y" connected stator coils, has circuitry for charging the coils at a rate which will reduce EMI and other noise, while maintaining an acceptable charge rate. The gate of a selected high side driving transistor is charged at a relatively high rate during a ramping phase. During the ramping phase, the gates of the selected transistor is charged to a voltage near the voltage needed to form a channel in the transistor for conduction. After the ramping phase, the gates are charged at a lesser rate in order to control the rate of charging of the stator coils to prevent noise.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A phase-locked loop (or frequency-locked loop) based circuit for controlling the drive applied to a DC polyphase motor is disclosed. The disclosed circuit includes a clamp circuit, connected to the input of the motor drive amplifier, for limiting the current applied to the drive amplifier, in order to ensure that the power supply is not overloaded. According to one embodiment of the invention, the clamp circuit includes a buffer amplifier having a source leg and a sink leg. During a current control mode, both the source leg and sink leg of the buffer amplifier are enabled to drive the input of the motor drive amplifier; the buffer amplifier is a differential amplifier and applies a feedback signal from the drive amplifier input to control the current applied thereto according to an input limit signal.

Abstract: A molded integrated circuit package system of the type suitable for surface mounting is disclosed. The system includes a chip package having leads along its sides that are of the surface-mountable type, and having a plurality of connectors at its ends. A module is provided which contains components that are sensitive to solder temperatures or the chemicals used in the soldering process; examples of such components include batteries and quartz crystal resonators. The components may be disposed directly over the chip package or, in order to reduce the height of the package system, one or both of the components may be disposed outside of the outline of the chip package. The module has connectors extending therefrom that mate with the connectors on the chip package, such that the module may be removably connected to the chip package after the surface mounting of the chip package to a circuit board.

Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device.

Abstract: A molded integrated circuit package system of the type suitable for surface mounting is disclosed. The system includes a chip package having leads along its sides that are of the surface-mountable type, and having a plurality of connectors at its ends. A module is provided which contains components that are sensitive to solder temperatures or the chemicals used in the soldering process; examples of such components include batteries and quartz crystal resonators. The module has connectors extending therefrom that mate with the connectors on the chip package, such that the module may be removably connected to the chip package after the surface mounting of the chip package to a circuit board. Mechanical connection may be provided by snap members extending from the module which engage surfaces of the chip package when mounted thereto. Lockout tabs are provided on the chip package and the module to prevent improper mounting and electrical connection.

Abstract: An output driver circuit for an integrate circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A memory cell having a first device operable to selectively conduct and coupled between a first cell node and a low voltage reference node and a second device operable to selectively conduct and coupled between a second cell node and the low voltage reference node. The memory cell further includes a first and second data line and circuitry for receiving a system level voltage and for biasing the first and second data lines at a first and second data voltage, respectively. Still further, the memory cell includes circuitry for coupling the first and second data line to the first and second cell node, respectively, such that a logical high voltage is selectively written to one of the first and second cell nodes while a logical low is written to the other of the first and second cell nodes during a write operation. Still further, the memory cell includes a voltage source node for receiving a cell voltage and circuitry for coupling the voltage source node to the first and second cell nodes.

Abstract: A bidirectional input/output buffer is disclosed, where the receiver includes complementary bus keeper transistors. The keeper transistors are of opposite conductivity types, and have their gates coupled to the output of a receiver inverter. The keeper transistors thus reinforce the driven data state at the input of the receiver, in CMOS latch fashion, and hold the prior data state thereon after the driving output driver is in tristate. The keeper transistors have significantly weaker drive characteristics than the other receiver transistors, and than typical output drivers, so that the keeper transistors can be easily overdriven with the next data state, if different. In addition, the source/drain resistance of the keeper transistors is also preferably quite high, so that the power dissipation on switching is relatively low. These characteristics are readily achievable by providing relatively long channel lengths for the keeper transistors, relative to other transistors in the circuit.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: A memory system includes two memory arrays coupled to a global data bus via respective address decode circuits. Address control circuitry defaults to the weaker memory array upon receiving a new address such that the stronger memory array will not produce false values on the bus prior to stabilization of the address and proper decode. Consequently, the weaker memory array is not faced with a situation where it must overcome the previous false signal prior to developing the proper output values on the bus.

Abstract: A method and circuit for operating a polyphase dc motor having a plurality of driving coils is presented. In one of the available operating modes, drive current supplied to the driving coils is chopped, in PWM fashion to control the maximum current delivered thereto by turning the drive current on and off. Zero crossings of a back emf voltage of the driving coils that are connected into a floating state are detected for producing a commutation signal, and the detection of zero crossings is inhibited for a predetermined time after the drive current is turned off during the chopping step to avoid detecting a false zero crossing. In normal operation, detected back emf sampled voltages are forwarded to back emf detection circuitry responsive to a high frequency clock.