Abstract: A method and circuit for braking a forward rotation of a rotor of a polyphase DC motor. A commutation sequencer is incremented by several phases to produce an incremented commutation sequence to produce a magnetic flux vector that lags a magnetic pole of the motor. Driving currents are applied to coils of the motor in accordance with the incremented commutation sequence to brake the rotor. The method is implemented in a circuit that has a sequencer for incrementally generating sets of commutation signals to select stator coils for energization to rotate the rotor. A power stage to which the commutation signals are applied energizes the selected coils in accordance with the commutation signals. A circuit interrupts the energization of the selected coils and the commutation sequence is altered to produce a sequence that produces a negative torque on the rotor.

Abstract: A circuit for sensing the current delivered to a load, or multiple loads, such presented by a polyphase DC motor, without significantly dissipating the energy delivered to the load, has a predriver circuit and a power delivery circuit for each load. The predriver circuit is connected in a series path between a voltage source and a control element of the power delivery circuit, and the power delivery circuit is connected between a connection node and a respective one of the loads. A sensing element is connected in a series path between the source of voltage and the power delivery circuit connection node. In a preferred embodiment, the sensing element is a resistor, the predriver circuit is a PNP transistor, and the power delivery circuit is an NPN transistor. The PNP and NPN transistors are connected to form a pseudo-Darlington transistor pair, with the collectors of the NPN transistors interconnected to enable a single sense resistor to be used to sense the current in each of the loads.

Abstract: A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor.

Abstract: A current source for producing a current that is proportional to absolute temperature (i.e., "PTAT") is disclosed. The current source is based upon a circuit having a pair of current mirrors, one based upon MOS transistors and the other based upon bipolar transistors, where each of two legs in the current source include the series connection of one of the MOS transistors with one of the bipolar transistors. Further included in the disclosed circuit is a series connection of three MOS startup transistors, useful in starting up the current source in a non-critical manner. A startup current source, sourcing a non-critical startup current, turns on one of the MOS startup transistors that is connected in current mirror fashion with the MOS transistor current mirror, turning on both current mirrors. As the output current increases, the current through the MOS startup transistors also increases, until equilibrium is achieved.

Abstract: Apparatus for displaying operating conditions of a device in which voltages that are produced when respective operating conditions exist are formed into a series of pulses with a bracket pulse on at least one end of the series and a display of indications of the presence of pulses at locations corresponding to their positions in the series.

Abstract: A semiconductor memory including test circuitry for directly determining the functionality of internal circuitry. The gates of test transistors are connected to the ends of signal lines in the memory, examples of which include bit lines, row or word lines, and control signal lines. Upon entry into a special test mode, the test transistors are biased to a voltage such that the active signal, if present, will turn on the test transistor and produce a signal indicating whether or not the active signal reached the test transistor. Multiple test transistors may be used to provide additional information, including the presence of short circuits, and the operation of multiple circuits within the memory.

Abstract: An apparatus for controlling a throttle of an internal combustion engine of a vehicle receives a signal related to an actual position of the throttle, and a target throttle position signal produced in response to a condition of the vehicle, such as loss of traction of one or more driving wheels. A polyphase motor is connected to control the position of the throttle. A circuit, such as a programmed digital computer, is also provided that is responsive to the target throttle position signal for simultaneously applying driving signals to at least two windings of the polyphase motor to cause the polyphase motor to move the position of the throttle until the signal related to the actual position of the throttle indicates that the throttle is at a position indicated by the target throttle position signal.

Abstract: A capacitive load driver is protected from short circuits to supply or to ground. The load driver includes an edge detecting monostable circuit and a plurality of sets of field effect transistor (FET) output devices, one set of the FET output devices having a low drain-to-source resistance and another set having a high drain-to-source resistance. The low resistance FET output devices provide a desired rise time voltage requirement on a capacitive load being driven. The high resistance FET output devices limit power dissipated under a short circuit to a predetermined amount.

Abstract: A circuit and method are provided for automatically adjusting a commutation delay from events indicating a position of a polyphase dc motor. The circuit includes a driver to supply drive current to selected stator coils of said motor. A sequencer is connected to control the driver to apply drive current to selected motor coils to rotate the motor. Motor position detecting circuitry is connected to detect the events indicating the position of the motor. A commutation delay circuit is connected to increment the sequencer in response to the detection of the events indicating the position of the motor detected by the motor position detecting circuitry. A circuit for adjusting the delay of said commutation delay circuit between each event and each sequencer commutation provides optimum motor commutation for maximum power efficiency.According to the method, drive current is supplied to selected stator coils of said motor in predetermined commutated sequences to rotate the motor.

Abstract: Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors.

Abstract: An integrated circuit memory having redundant rows, for replacing a row in a primary array having a defective memory cell, is disclosed. For each primary row that is to be replaced, a fuse is opened between the output of the row decoder and the word line for the replaced row. A power-on reset circuit is provided in the memory for determining if the power supply voltage has reached an adequate voltage; if not, a transistor connected to each word line is turned on, biasing the word line to a de-energizing voltage. This ensures that the word lines for replaced rows do not power up in an "on" state.

Abstract: A biasing device which is in thermal contact with an RF device for actively biasing the RF device operating in quasi-linear modes. The biasing device provides a low impedance current source with high current capability to the base of the RF device. The biasing device includes three specially-processed transistors. The second and third transistors are connected such that their base-emitter and base-collector junctions are in parallel effectively forming two exceptionally low turn on series diodes. The result of reducing the resistances of the second and third transistors, by configuration and processing, is that they turn on slightly before the RF device is biased to its quiescent point.

Abstract: A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

Abstract: A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface.

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device.

Abstract: An integrated circuit package of the surface-mountable type within which a battery is mounted is disclosed. Battery leads extend from the side of the package body opposite that which is adjacent the circuit board when mounted, and between which a conventional battery may be placed. Standoffs are located on the package body for supporting the battery above the package body, so that a gap is present therebetween. A housing is attached to the package over the battery, and has standoffs attached to its inner surface so that a gap is also present between the housing and the battery. The gaps may be air gaps or filled with a low thermal conductivity material. The gaps thermally insulate the battery from the package body and housing, so that the circuit may be subjected to solder reflow mounting to a circuit board, while insulating the high temperatures from the battery.