Abstract: Described is a system designed to control the slit valve used to isolate chambers in cluster tools used in integrated circuit (IC) fabrication. This method changes the slit valve door actuator pneumatic pressure and movement during the closing sequence. As the door nears the fully closed position, its speed is reduced. This results in a soft touch landing or seating of the door and reduces the number of particles generated over systems incorporating higher pressure in the door closure. Once the door is seated in a fully closed position, higher pressure is applied to maintain a tight seal between chambers. By reducing the particles generated, the overall IC yield for both production and test wafer lots will improve. Reducing wear on the door and door seat, fewer parts such as the door, door seat and slit valve O-ring are consumed, and both scheduled and unscheduled maitenance times are shortened.

Abstract: A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Abstract: A new method is provided for the polishing of semiconductor surfaces such as the surface of a substrate, the surface of deposited copper and the surface of low-k layers of dielectric. The polishing method and apparatus of the invention comprise a new slurry delivery design whereby at least two different slurries can be independently controlled and mixed for delivery to a slurry container. The slurry container is in direct physical contact with a polishing pad, providing for the mixed slurry to be distributed over the surface of the polishing pad.

Abstract: A new method of preventing photoresist footing by forming a silicon oxynitride ARC layer having an oxygen-rich surface is described. An insulating layer is provided on a substrate. A metal layer is deposited overlying the insulating layer. A silicon oxynitride antireflective coating layer having an oxygen-rich surface is deposited overlying the metal layer. A photoresist mask is formed overlying the antireflective coating layer wherein the antireflective coating layer prevents photoresist footing. The antireflective coating layer and the metal layer are etched away where they are not covered by the photoresist mask to complete formation of metal lines in the fabrication of an integrated circuit.

Abstract: A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.

Abstract: A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.

Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.

Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A novel method for forming short channel MOS transistors is described. A hard mask stack is formed over a substrate. A first opening is formed through a top portion of the hard mask stack. Oxide spacers are formed on sidewalls of the first opening thereby forming a second opening smaller than the first opening. The second opening is filled with a polysilicon layer. Thereafter, the oxide spacers are removed. First ions are implanted into the substrate underlying the removed oxide spacers to form source/drain extensions. Then, the polysilicon layer is removed wherein the first opening remains and wherein the substrate is exposed in a channel region. A gate dielectric layer is formed over the channel region. The first opening is filled with a gate electrode material that is polished back to form a gate electrode. The hard mask stack is removed using the gate electrode as a mask.

Abstract: One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.

Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

Abstract: A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer.

Abstract: A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which has a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting slots and wafer supporting means engaging the periphery of each wafer in an individual slot with the central axis of all wafers in coaxial alignment. A supporting platform is placed over the cassette for supporting the wafers in an inverted position in which the wafers are substantially vertical and biased by their own weight against a multiplicity of orienting mechanisms. The orienting mechanisms are arranged to correspond to each wafer position within the cassette. The plurality of orienting mechanisms are integrated with the supporting platform so that all wafers within the cassette can be aligned during this aligning process.

Abstract: A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage.

Abstract: A two step passivation procedure, used to remove chlorine from polymer layers formed on the sides of metal structures, prior to removal of the defining photoresist shape, and of the polymer layers, has been developed. The procedure features a first passivation step, performed at a low substrate temperature, (100-140° C.) at low RF power, (150 to 250 watts), and using a 2 to 1 ratio of oxygen to water, resulting in removal of corrosion causing chlorine, from the polymer layers, located on the sides of a first group of defined metal structures, which in turn reside at the edge of a semiconductor substrate. A second passivation step, of the two step passivation procedure, is then performed using water only, at higher substrate temperature, (200-250° C.), resulting in removal of chlorine from polymer layers located on the sides of a second set of metal structures, which reside at the center of the semiconductor substrate.