Abstract: An apparatus for multiple component slurry distribution during semiconductor wafer polishing operations. Concurrent polishing pad conditioning is obtained by means of a novel polishing pad design where polishing pads are mounted in a cylindrical configuration as opposed to the conventional flat surface configuration. A polishing pad conditioner is provided to refurbish the polishing pad.

Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.

Abstract: A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.

Abstract: A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

Abstract: A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

Abstract: A method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is described. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein after a time period, copper flakes form on the surface of the copper and dielectric layers.

Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.

Abstract: A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions.

Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accomodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.

Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.

Abstract: The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

Abstract: A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.

Abstract: A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections.

Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.

Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.

Abstract: A method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is deacribed. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. Openings are etched through a second insulating layer to each of the node contact plugs. A polysilicon layer is conformally deposited within the openings and then recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors.

Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

Abstract: A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed.