Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract: A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

Abstract: A carrier head is provided that improves the pressure uniformity of a semiconductor wafer against the polishing pad in chemical mechanical polishing (CMP). The carrier head includes a carrier, a carrier film, and a guide ring. The objective of CMP is to provide planarization of the surface of a semiconductor wafer by uniformly removing material. One embodiment of the invention uses independent adjusting screws threaded in the carrier to provide uniform wafer pressure and lengthen guide ring life. The adjusting screws are threaded internally to accept holding screws attached to the guide ring using a backing. This facilitates variation in the spacing between the carrier and guide ring at each adjusting screw. A locking nut on each adjusting screw is used to maintain each gap setting. This embodiment eliminates the need for shims and the associated trial-and-error set-up time in selecting shims. In addition, compensating for guide ring wear can be easily performed without disassembling the carrier head.

Abstract: A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. The second dummy gates and spacers are removed. A first metal layer is deposited overlying the substrate and patterned to form a first metal gate in one of the NMOS and PMOS active areas.

Abstract: A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.

Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.

Abstract: A method of forming shallow trench isolation using CMP is described. A pad oxide layer is grown overlying a silicon semiconductor substrate. A polysilicon layer and a nitride layer are deposited. Trenches are etched through the nitride layer, polysilicon layer, and pad oxide layer into the silicon semiconductor substrate and filled with an oxide layer. A silicon oxynitride layer is deposited overlying the oxide layer. A first polishing is performed to polish away the silicon oxynitride layer and oxide layer using a first slurry having high selectivity of oxide to nitride. A second polishing is performed to polish away the oxide layer using a second slurry having a low selectivity of oxide to nitride. The nitride layer is removed and a third polishing is performed to planarize the oxide layer using a third slurry having high selectivity of oxide to polysilicon.

Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.

Abstract: A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

Abstract: A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created. Under the first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited, The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched. Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.

Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.

Abstract: A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. A polysilicon layer is formed over the first gate oxide layer. A patterned oxide mask and photoresist layer are formed over the polysilicon layer within the gate conductor region leaving unmasked polysilicon layer portions and unmasked first gate oxide layer portions. An oxygen implant is conducted within the unmasked polysilicon layer portions proximate the unmasked first gate oxide layer portions. The patterned photoresist mask is removed. The structure is annealed to form second gate oxide portions within the unmasked polysilicon layer portions over the unmasked first gate oxide layer portions.

Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant or ferroelectric interelectrode films compatible with the dual-damascene process is achieved. The method of integrating the MIM with a dual-damascene process is to form a planar a first insulating layer and to deposit an etch-stop layer and a second insulating layer. Capacitor node contact openings are etched to the substrate and first recesses are etched to the etch-stop layer. The contact openings and first recesses are filled with a conducting layer using a dual-damascene process. Second recesses are formed in the second insulating layer around the capacitor node contacts. A conformal first metal layer, an interelectrode dielectric layer, and a second metal layer are deposited, and are patterned at the same time to form the capacitors over the node contacts. The second recesses increase the capacitor area while the simultaneous patterning of the metal layers results in fewer processing steps.

Abstract: A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.

Abstract: A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

Abstract: A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.