Abstract: Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.

Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.

Abstract: A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate.

Abstract: A double acting cold trap equipped with a set of exhaust gas condensing fins and a set of exhaust gas condensing plates is disclosed. The invention also discloses a double acting cold trap that incorporates a deflecting plate to direct the exhaust gases over the condensing fins and plates in a serial fashion. This increases the efficiency of the collection of unwanted particles.

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is described. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer and filled with a silicon layer to form a deep trench capacitor. A polysilicon layer is deposited over the capacitor to form a buried strap. A liner layer is deposited over the etch stop layer and the buried strap having the same material as the etch stop layer. A hard mask material is deposited over the liner layer and etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches.

Abstract: Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450° C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity.

Abstract: A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

Abstract: A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.

Abstract: A method for controllably simultaneously polishing polysilicon and oxide using an oxide slurry and a polish stop layer over the oxide is described. Semiconductor device structures are provided in and on a semiconductor substrate. An oxide layer is deposited overlying the semiconductor device structures. A silicon nitride layer is deposited overlying the oxide layer as a polish stop layer. A contact opening is etched through the silicon nitride layer and the oxide layer to one of the semiconductor device structures. A polysilicon layer is deposited overlying the silicon nitride layer and within the contact opening. The polysilicon layer is polished until the silicon nitride layer is contacted and then the polysilicon layer, silicon nitride layer, and oxide layer are overpolished in a timed polish to remove the silicon nitride layer and planarize the oxide layer to complete simultaneous planarization of the oxide and polysilicon layers in the fabrication of an integrated circuit device.

Abstract: An apparatus for closed loop slurry distribution during semiconductor wafer polishing operations. The traditional peristaltic pump for slurry supply is eliminated thus eliminating irregularities in the conventional slurry supply. Common platform mounting of the slurry reservoir and the polishing apparatus resulting in concurrent and identical motion of the slurry supply reservoir and the polishing apparatus. The polishing medium is mounted on the outside of a cylinder as opposed to the conventional table mounting, the polishing medium rotates around the axis of the cylinder on which this polishing medium is mounted. The polishing pads are in direct physical contact with the slurry supply without the intervention of any slurry pumping arrangement.

Abstract: A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer.

Abstract: An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for “zero” spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as “standard” logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability.

Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A new apparatus is provided for the quantification of the adhesion of a film over a substrate. In particular, the peeling force and the rate of peeling are quantified by providing a first means for measuring the peeling force, a second means for measuring the rate of peeling, a third means for securing a piece of wafer, an adhesive tape, a tape holder and a resilient, flexible component.

Abstract: A new method of forming a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first planarized photoresist layer which is baked. The first photoresist layer is coated with a second silicon-containing photoresist layer which is baked. Portions of the second photoresist layer not covered by a mask are exposed to actinic light. The exposed portions of the second photoresist layer are developed away. Then, portions of the first photoresist layer not covered by the second photoresist layer remaining are developed away in a dry development step wherein sufficient SO2 gas is included in the developing recipe to reduce microloading to form a bi-layer photoresist mask comprising the first and second photoresist layers remaining.

Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: A method for forming a stack DRAM cell with CUB wherein coupling noise is eliminated is described. Bit-lines are formed according to one of three methods. In a first method, a first pair of bit-lines is fabricated in a first metal layer and a second pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first pair of bit-lines is horizontally spaced from the second pair of bit-lines. In a second method, a first of each pair of bit-lines is fabricated in a first metal layer and a second of each pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines. In a third method, each bit-line is divided into segments.