Abstract: A PMR writer having a trailing shield structure is disclosed in which a flux choking layer (FCL) formed adjacent to the ABS provides a means to limit the amount of flux flowing from the trailing shield to a first write shield (WS1) near the write pole tip thereby significantly reducing adjacent track erasure. The FCL has a substantially smaller thickness than a top section of the trailing shield to which it is attached along a side opposite the ABS. As a result, pole tip protrusion is reduced compared to prior art PMR writers. The FCL contacts a trailing side of WS1 at the ABS and one or both of the trailing sides of the WS1 and FCL may be tapered or perpendicular with respect to the ABS. The top trailing shield section, FCL, and WS1 may be comprised of NiFe, CoFe, CoFeNi, or alloys thereof.

Abstract: The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode.

Abstract: Disposable units in current use for performing PCR are limited by their heat block ramping rates and by the thermal diffusion delay time through the plastic wall as well as by the sample itself. This limitation has been overcome by forming a disposable plastic chip using a simple deformation process wherein one or more plastic sheets are caused, through hydrostatic pressure, to conform to the surface of a suitable mold. After a given disposable chip has been filled with liquid samples, it is brought into close contact with an array of heating blocks that seals each sample within its own chamber, allowing each sample to then be heat treated as desired.

Abstract: A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: Circuits and methods to read out capacitive sensors for distance measurement used by a position control system having a high accuracy and low noise have been disclosed. The ratio or difference of the capacitances of two sensor capacitors is used to determine the distance of an object from a target position. A sense amplifier is using auto-zero methods to achieve a long term stability. A sample-and-hold circuit using double correlated sampling methods minimizes noise. Low cost capacitors can be used with the sample-and-hold circuit because not the absolute value of capacitances but only the ratio of capacitances are relevant. A high resolution is ensured also by significant over-sampling of the control loop.

Abstract: A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Abstract: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.

Abstract: A folded cascode receiver amplifier with constant gain has inputs coupled to PMOS and NMOS differential transistors pairs with scaled geometries. The transconductance of both PMOS and NMOS transistors is the same whether the common mode input voltage is low or high. In a first version the transconductance of both PMOS and NMOS differential transistor pairs is reduced when the common mode input voltage is at mid-rail. Resistive means between current sources and the sources of the PMOS and NMOS transistor pairs force the current source transistors into the triode region of operation. A second version insures a constant voltage gain through control means which maintain a constant ratio of the transconductance of the output stage transistors versus the PMOS and NMOS differential transistor pairs when active.

Abstract: An image is focused onto an image sensor array by efficient movement of an adjustable focus lens by a lens focus motor. A minimum of three focus positions is required to determine an estimated best focus position of the lens focus motor. After which a sweep of the focus positions surrounding the estimated best focus position is performed to verify and determine the best actual focus position of the lens focus motor. A sharpness value of the image being focused comprising a Sobel edge detection or other detections means provide sharpness data to evaluate image sharpness at various lens focus motor positions.

Abstract: A spin valve structure for a spintronic device is disclosed and includes a composite seed layer made of at least Ta and a metal layer having a fcc(111) or hcp(001) texture to enhance perpendicular magnetic anisotropy (PMA) in an overlying (Co/Ni)x multilayer. The (Co/Ni)x multilayer is deposited by a low power and high Ar pressure process to avoid damaging Co/Ni interfaces and thereby preserving PMA. As a result, only a thin seed layer is required. PMA is maintained even after annealing at 220° C. for 10 hours. Examples of GMR and TMR spin valves are described and may be incorporated in spin transfer oscillators and spin transfer MRAMs. The free layer is preferably made of a FeCo alloy including at least one of Al, Ge, Si, Ga, B, C, Se, Sn, or a Heusler alloy, or a half Heusler alloy to provide high spin polarization and a low magnetic damping coefficient.

Abstract: A harvester and method for harvesting aquatic algae or floating vegetation in shallow areas of water bodies, such as lakes. The harvester is manually operated. The harvester includes a pair of blades which are manually moved by a rope connected to an extension spring, a compressed gas cylinder or the harvester wheels through a metal rod driven system. The harvester provides improved hydraulic flow through a hydraulic friction reducing plastic or metal sheet, a movable plastic or metal bar to adjust the volume of water allowed into the apparatus and vertical hydraulic flow guides to improve flow of water through the apparatus. The aquatic algae or floating vegetation is collected on the harvester, removed from the harvester, dewatered and used for compost in garden and agricultural activities.

Abstract: In a read-write head, the shields can serve as magnetic flux conductors for external fields, so that they direct a certain amount of flux into the recording medium. This problem has been overcome by the addition to the shields of a pair of tabs located at the edges closest to the ABS. These tabs serve to prevent flux concentrating at the edges so that horizontal fields at these edges are significantly reduced. The tabs need to have aspect ratios of at least 2 and may be either triangular or rectangular in shape. Alternatively, the tabs may be omitted and, instead, outer portions of the shield's lower edge may be shaped so as to slope upwards away from the ABS.

Abstract: We describe a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel synthetic free layer having three ferromagnetic layers mutually exchange coupled in pairwise configurations. The free layer comprises an inner ferromagnetic and two outer ferromagnetic layers, with the inner layer being ferromagnetically exchange coupled to one outer layer and anti-ferromagnetically exchange coupled to the other outer layer. The ferromagnetic coupling is very strong across an ultra-thin layer of Ta, Hf or Zr of thickness preferably less than 0.4 nm.

Abstract: A PMR head comprises a substrate, a magnetic pole formed over the substrate, the pole having a pole tip having a cross-sectional tapered shape wherein the pole tip is surrounded by a write gap layer, an integrated shield comprising side shields on the substrate laterally surrounding the pole tip and a trailing shield overlying the pole tip and integral with the side shields.

Abstract: In a method of vacuum packaging a MEMS device, at least one MEMS device is attached on a substrate. A solder preform is printed on the substrate at the perimeter surrounding the substrate. A lid is attached to the solder preform wherein the lid provides a cavity enclosing the at least one MEMS device. A first reflowing step reflows the solder at a first temperature, partially sealing the lid/substrate interface and at the same time does the outgassing and baking procedure for the packaging. Flux is applied onto an outer ring of the solder preform and a second step reflows the solder at a second temperature, completely sealing the lid/substrate interface and providing a vacuum cavity enclosing the at least one MEMS device.

Abstract: A composite free layer having a FL1/insertion/FL2 configuration is disclosed for achieving high dR/R, low RA, and low ? in TMR or GMR sensors. Ferromagnetic FL1 and FL2 layers have (+) ? and (?) ? values, respectively. FL1 may be CoFe, CoFeB, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, or Nb. FL2 may be CoFe, NiFe, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, Nb, or B. The thin insertion layer includes at least one magnetic element such as Co, Fe, and Ni, and at least one non-magnetic element selected from Ta, Ti, W, Zr, Hf, Nb, Mo, V, Cr, or B. In a TMR stack with a MgO tunnel barrier, dR/R>60%, ?˜1×10?6, and RA=1.2 ohm-um2 when FL1 is CoFe/CoFeB/CoFe, FL2 is CoFe/NiFe/CoFe, and the insertion layer is CoTa or CoFeBTa.

Abstract: Biasing schemes used for CIP GMR devices were previously thought to be impractical for CPP devices due to current shunting by the abutted hard magnets. In the present invention the CPP stripe is a narrow conductor directly above the free layer. The resistivity of the latter is made to be relatively high so the sensing current diverges very little as it passes through it. This makes it possible to use abutted hard magnets for longitudinal bias with virtually no loss of sensing current due to shunting by the magnets.

Abstract: A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.

Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.