Abstract: A method and system for utilizing a completion table in a superscalar processor is disclosed. The method and system comprises providing a plurality of threads to the processor and associating a link list with each of the threads, wherein each entry associated with a thread is linked to a next entry. A method and system in accordance with the present invention implements the completion table as link lists. Each entry in the completion table in a thread is linked to the next entry via a pointer that is stored in a link list. In a second aspect a method of determining the relative order between instructions is provided. A method and system in accordance with the present invention implements a flush mask array which is accessed to determine the relative order of entries in the said completion table. A method and system in accordance with the present invention implements a restore head pointer table to save and restore the state of the pointer of said completion table.

Abstract: Aspects of failure detection of an isolation device in a power supply of a redundant power supply system are described. The aspects include an isolation device coupled to a voltage input line of a power supply. A comparator coupled to the isolation device provides a predictive failure analysis (PFA) signal when the isolation device fails.

Abstract: A system and method for providing a trusted machine state in a data processing system is disclosed. The data processing system includes a memory. The trusted machine state is stored in a first portion of the memory. The method and system include saving the trusted machine state in a second portion of the memory and reinitializing a portion of the memory. The portion of memory is separate from the second of memory. The method and system further include restoring the trusted machine state in the memory. According to the method and system disclosed herein, the data processing system may recover from failures and resume operation. Moreover, a non-disruptive code load, in which a new program can be loaded without disrupting system operations, may be performed.

Abstract: A method and system for providing visual hierarchy of task groups and related viewpoints of a three dimensional display of a computer system is disclosed. The method and system comprises providing a group of task related objects and positioning an object within an associated viewpoint when the object is to be utilized. In the present invention each task group is composed of objects related to a particular user task. Associated with each task group is a viewpoint in the 3D space. The visual organization of task groups and associated viewpoints allows the user to traverse the task-object hierarchy smoothly, seeing more or less of the surrounding task context as desired.

Abstract: The present invention provides method and system aspects for performing error data gathering from fault isolation registers of a computer system following a machine check occurrence. A method aspect includes utilizing firmware to perform failure information retrieval in software accessible registers and initiating a service processor (SP) for failure data retrieval in non-software accessible registers. The method further includes coordinating the combination of the failure information retrieved and the failure data retrieved in an error log for use in isolation of a fault source in the computer system.

Abstract: A method and system for classifying user objects in a three-dimensional environment on a display of a computer system is disclosed. The method and system comprises providing a set of standardized classes of user objects and defining the standardized classes based upon a users needs. The method and system is directed toward a classification for objects relevant to the tasks of organizing the 3D environment, navigating through the 3D environment, and performing useful work in the 3D user environment in a computer system classification. The distinction between classes of objects in the classification is based on user needs and is reflected in the properties and behaviors of objects as perceived by the users.

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75% and also synchronize the MAC/PHY interface.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.

Abstract: The present invention provides a method and system for porting an integrated circuit layout from a reference process to a target process. The method and system comprises placing components related to the reference process on a grid, wherein the grid is determined by equations that are based upon the desired layout architecture. The method and system includes utilizing the design rules of the target process along with the equations to determine the grid of the target process. The component layout is controlled by parameters, where the design rules provide the values of the parameters. Thus, each component will be properly ported when the parameter values are changed to that of the target process. Finally, the locations of the components are mapped grid-point to grid-point from the reference process to the target process. In so doing, an integrated circuit layout in the target process is drawn without design rule violation.

Abstract: A system and method for monitoring a wavelength of light produced by a light source is disclosed. The system and method comprise a diffractor for diffracting the light. A first portion of the light is transmitted without diffraction and has a propagation direction. A second portion of the light has a predetermined wavelength and is diffracted through a predetermined angle from the propagation direction. The system also comprises a plurality of filters at the predetermined angle from the propagation direction from the diffractor. The filters transmit light of the predetermined wavelength. The system also comprises a plurality of photodiodes. Each photodiode provides a signal corresponding to an intensity of light and corresponds to a one of the plurality of filters. Each photodiode is placed behind a corresponding filter. According to the system and method disclosed, the system and method monitor the wavelength without significant interruption of the beam.

Abstract: The present invention provides a method and system for providing an improved view of an object on a display in a computer system, via a user event. The method comprises the step of providing a three-dimensional environment on the display, the three-dimensional environment including a plurality of objects, each of the plurality of objects appearing to be three-dimensional. The method and system further comprises providing a two-dimensional representation of at least one of the plurality of objects responsive to the user event.

Abstract: Aspects for supporting a package and a device coupled to the package at a device frontside during package removal at a package backside are described. In an exemplary aspect, a support structure includes a support frame supporting the package substantially near end portions of the package, and a set of support braces supporting the package substantially near the device. The structure further includes a block support positioned within the set of support braces and substantially underneath the device at a predetermined distance from the device. Support material is provided between the support frame and the set of support braces and between the block support and the device, wherein breakage of the package during grinding removal of the package is reduced.

Abstract: A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing.

Abstract: A system and method for providing a high speed differential receiver circuit is disclosed. The system comprises a source device. A receiver is coupled to the source device. The receiver receives first and second differential signals at a first input and a second input and provides first and second output signals at a first output and a second output. The system also comprises a first plurality of load devices coupled to the first output. The first plurality of load devices control a first voltage swing at the first output. The system also comprises a second plurality of load devices coupled to the second output. The second plurality of load devices control a second voltage swing at the second output.

Abstract: A system of supporting differential signalling circuitry in an enhanced PCI bus within a data processing system is disclosed The enhanced PCI bus comprises a plurality of differential signal conductor pairs. A system and method in accordance with the present invention comprises a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end. The system and method includes a differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states, a receiver for sensing a voltage change between the first line and the second line and a termination network coupled to the first line and second line for terminating the first line and the second line.

Abstract: A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.

Abstract: Method and system aspects for monitoring computer system operations are provided. A computer system including a processor, the processor supporting firmware and a running operating system, and a service processor coupled to the processor, is monitored by initiating surveillance of the computer system in the firmware when an architected function occurs in the operating system. Monitoring additionally includes providing a pulse indicator from the firmware to the service processor and determining a status of computer system operations with the service processor based on a frequency of the pulse indicator.

Abstract: Method and system aspects for allowing user control of data transfer from websites on the Internet via a web browser on a client system are presented. A method aspect includes establishing limits for allowable connections in the client system, and communicating the limits from the client system to a server system hosting a selected website. The method further includes comparing within the server a current transfer session to the communicated limits for allowable connections, and controlling the current transfer session by the server according to comparison results.A system for allowing user control of data transfer from websites on the Internet includes a client system, the client system requesting connection to a remote website with established limits.