Patents Represented by Attorney, Agent or Law Firm Sawyer & Associates
  • Patent number: 6015736
    Abstract: A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: January 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott D. Luning, Mark Randolph
  • Patent number: 6016308
    Abstract: A method and system for providing statistical network information carried in a data packet being transmitted on a network. The method includes the steps of receiving a data packet having a data portion on a repeater and transferring the data portion to a management unit. The method further includes the step of appending statistical information to the data portion during an inter-packet gap period. The apparatus for increasing information in a data packet on a network includes a repeater mechanism, a management unit mechanism, and a packet tagging circuit. The repeater mechanism receives a data packet having a data portion, the management unit mechanism determines statistical information based on the data packet, and the packet tagging circuit appends information to the data portion of the data packet during an inter-packet gap period.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: January 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ian S. Crayford, William Lo
  • Patent number: 6010960
    Abstract: A system and method for providing an interconnect on a substrate is disclosed. The method and system include providing a first layer, a first barrier layer, and a second layer. The first layer is subject to electromigration and has a thickness. The thickness of the first layer is smaller than what is required to support formation of a void. The first barrier layer is resistant to electromigration. The first barrier layer is disposed between the first layer and the second layer. In a second aspect, the method and system include providing a first layer and a first barrier layer. The first layer is subject to electromigration and has a thickness. The thickness of the first layer is smaller than what is required to support formation of a void. The first barrier layer is resistant to electromigration.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: January 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Takeshi Nogami
  • Patent number: 6009246
    Abstract: The present invention discloses a system and method to evaluate intrusive repair. The method and system is based on analyzing data from the field and drawing causal diagrams (cause-consequence diagrams). In an aspect of the present invention, a method and system for evaluating intrusive repair for a class of devices comprises providing a threshold time window for analyzing failure data. The system and method further includes utilizing a causal diagram based on the analysis of the failure data for the class of devices to indicate the probability of intrusive repair. In the present invention, two measures are defined to evaluate intrusive repair--intrusivability and one-fixability. Intrusivability is defined as the probability that a repair action will cause a new fault. One-fixability is defined as the probability that the diagnostic process will fix the fault on the first repair attempt. Both of these measures are determined by using the causal diagram in accordance with the present invention.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 28, 1999
    Assignee: International Business Machines Corporation
    Inventors: Arun Chandra, John Carl Grzinich, Manoranjan Kanthanathan
  • Patent number: 6005409
    Abstract: A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: December 21, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nguyen D. Bui, Chenming Hu, Donggun Park, Scott Zheng
  • Patent number: 6006345
    Abstract: A system and method for testing of a memory during burn-in is disclosed. In one aspect, the method and system include an address generator. The address generator includes a shift register means. The shift register includes n bit positions. The n bit positions are for storing n bits. The n bits are capable of being in a plurality of patterns. The address generator further includes a counter coupled to the shift register means. The counter includes a value that is incremented in response to a particular pattern of the plurality of patterns. The address generator has a complement mechanism coupled to the shift register and the counter which provides a complement of at least a portion of the n bits stored in the n bit positions in response to the value in the counter. In another aspect, the method and system comprise the address generator previously discussed coupled to the memory undergoing testing.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: December 21, 1999
    Assignee: International Business Machines Corporation
    Inventor: Robert W. Berry, Jr.
  • Patent number: 6002436
    Abstract: The present invention provides a system and method for timelapse capture in an image capture unit. A system and method for timelapse capture according to the present invention comprises capturing a first image automatically; initiating a sleep mode after capturing the first image; and transitioning from the sleep mode into a wake mode prior to capturing a second image. According to the present invention, a system and method is provided which provides a digital camera with the ability to automatically place the digital camera in a sleep mode during the interval when the camera is inactive. The sleep mode minimizes power consumption during inactive periods of a timelapse capture sequence, thus allowing automation of timelapse sequences. The sleep mode can be initiated if a predetermined time interval is greater than a setup time required prior to initiating the next image capture.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: December 14, 1999
    Assignee: FlashPoint Technology, Inc.
    Inventor: Eric C. Anderson
  • Patent number: 5998301
    Abstract: A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 7, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tuan D. Pham, Angela T. Hui, Kashmir Sahota
  • Patent number: 5999177
    Abstract: The present invention provides a method and system for controlling content on a display of a computer system. The method and system comprises providing at least one control element on the display, moving the at least one control element selectively between a first position and a second position on the window. The method and system further includes the content between the first and second positions. The at least one control element allows the user to "fold" windows of information like a piece of paper, at any location, to hide information that is not of interest to the user.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: December 7, 1999
    Assignee: International Business Machines Corporation
    Inventor: Anthony Edward Martinez
  • Patent number: 5994206
    Abstract: A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: November 30, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Subhash Gupta, Susan Hsuching Chen
  • Patent number: 5995514
    Abstract: A reversible media independent interface (MII) circuit is disclosed. The MII circuit comprises a first management circuit and a second management circuit. The first management circuit is operating in a first mode, the first mode being an interface between the MII and a media access control (AC) device. The second management circuit is operating in a second mode, the second mode being an interface between the MII and a physical layer (PHY) device. The MII circuit also includes a plurality of signals being provided to and sent from the MII circuit. A first portion of the plurality of signals are operable within either a physical layer device in a first mode or a media access control device in a second mode. A second portion of the plurality of the signals are provided the first management circuit and the second management circuit.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: November 30, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William Lo
  • Patent number: 5995555
    Abstract: A precoded waveshaping transmitter comprises a synchronous delay line circuit, a transmitter state machine and a differential current digital to analog converter. Through the provision of a plurality of precoded staggered time delayed data from the combination of the delay line circuit and transmitter state machine the DAC can provide a predetermined output. In a preferred implementation, a subharmonic frequency can be maintained at least 27dB below the fundamental frequency when the PWT is driven by an all ones Manchester encoded signal.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: November 30, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David Young
  • Patent number: 5988892
    Abstract: A system and method for providing an optical coupler is disclosed. In one aspect, the method and system include a plurality of optical fibers, a first covering, and a second covering. The plurality of optical fibers further include a first end, a second end, a fused portion between the first end and the second end, a first interface between the first end and the fused portion, and a second interface between the second end and fused portion. The first and second coverings enclose substantially all of the first and second interfaces, respectively. In a second aspect, the method and system include a plurality of optical fibers and a covering. The plurality of optical fibers further include a first end, a second end, a fused portion between the first end and the second end, a first interface between the first end and the fused portion, and a second interface between the fused portion and the second end. The covering encloses substantially all of the fused portion, the first interface, and the second interface.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Oplink Communications, Inc.
    Inventors: Xiaobing Luo, Yu Zheng
  • Patent number: 5991465
    Abstract: Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: November 23, 1999
    Assignee: Apple Computer, Inc.
    Inventors: Eric C. Anderson, Gary Chin
  • Patent number: 5987974
    Abstract: The present invention provides a portable cylinder contribution tester for an electronic diesel engine, the diesel engine including a plurality of cylinders. The tester comprises a plurality of switches, each of the plurality of switches coupled to and for controlling one of the plurality of cylinders and a case for mounting the plurality of switches. When an abnormal diesel engine operation is detected each of the plurality of switches can be activated. When one of the plurality of switches is activated and the diesel engine does not decrease in performance it is indicated that the associated cylinder is malfunctioning. Existing test equipment for most electronic diesel engines is PC based and available to franchised dealers only, as well as not being portable for drive testing. Through the use of a cylinder contribution tester in accordance with the present invention, these type of repairs could be available to many independently owned non-franchised facilities.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: November 23, 1999
    Assignee: Mission Valley Ford Truck Sales, Inc.
    Inventors: John Joseph Lewis, Glen Thomas Hart
  • Patent number: 5986477
    Abstract: A system and method for providing a plurality of interconnects for a microcircuit is disclosed. The microcircuit has a plurality of functional components. The method and system include determining the placement of each of the plurality of functional components and determining a width of each of the plurality of interconnects. The determination of the width is based on a capacitance between each interconnect and a portion of the plurality of interconnects.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chun Jiang, Linda Milor
  • Patent number: 5986472
    Abstract: Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: November 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Fahd Hinedi, Moises Cases, Satyajit Dutta, Robert Heath Dennard
  • Patent number: 5986329
    Abstract: The present invention provides a method and system for depositing an oxide layer onto a semiconductor device during fabrication by using a deposition chamber, the method comprising the steps of providing a temperature of less than approximately 450 degrees Celsius in the deposition chamber; allowing the semiconductor wafer to soak up the temperature of less than approximately 450 degrees Celsius for approximately 30 seconds; and depositing a layer of oxide onto a semiconductor wafer, wherein a thickness of the oxide layer is not greater than approximately 200 Angstroms.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Minh Van Ngo
  • Patent number: 5986701
    Abstract: A method for grouping related images captured with an image capture device includes identifying a first group, the first group distinguishing at least one first image of an image capture method defined in the image capture device, and identifying a second group, the second group distinguishing at least one second image of one or more designated image characteristics, wherein the first and second groups provide structured relationships among images. The first group further includes a natural group and the image capture method further includes a time lapse capture. A system includes a digital image capture device, the digital image capture device capable of capturing and processing digital image data, and a central processing unit within the digital image capture device. The central processing unit further coordinates identification of a first group and identification of a second group, wherein the first and second groups provide structured relationships among images.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: November 16, 1999
    Assignee: Flashpoint Technology, Inc.
    Inventors: Eric C. Anderson, Mike Masukawa
  • Patent number: D418826
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: January 11, 2000
    Assignee: FlashPoint Technology, Inc.
    Inventors: John F. Pavely, Edgar Y. Lee, Eric C. Anderson