Abstract: A monolithic integrated multiple mode circuit having an output stage, a transfer gate, a control circuit arrangement, and a well contacting region where a well potential may be applied, the multiple mode circuit adapted to be controlled into an output stage mode or an input stage mode by means of control data.

Abstract: A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus distributing an array supply voltage to the array, and a control circuit power bus distributing a control circuit supply voltage to the control circuits. Regulator circuits are coupled to the array power bus at spaced-apart locations along the bus which allow each regulator circuit to respond independently to a localized variation in the array supply voltage. Other regulator circuits are similarly coupled to the control circuit power bus. The regulator circuits which are unneeded for a particular operating mode of the memory device can be turned off during active memory cycles, and all the regulator circuits can be turned off during stand-by memory cycles.

Abstract: An adjustable coupler has a group of magnet rotors with permanent magnets separated by air gaps from non-ferrous conductor elements presented by a group of conductor rotors. The air gaps are adjusted by axial movement of one of the groups relative to the other to vary the slip of the coupler and control the load speed under varying load conditions.

Abstract: A pad refurbisher that provides in situ, real-time conditioning and/or cleaning of a polishing surface on a polishing pad used in chemical-mechanical polishing of a semiconductor wafer and other microelectronic substrates. The pad refurbisher has a body adapted for attachment to a wafer carrier of a chemical-mechanical polishing machine, and a refurbishing element connected to the body. The body has a distal face positioned proximate to a perimeter portion of the wafer carrier and facing generally toward the polishing surface of the polishing pad. The body travels with the wafer carrier as the wafer carrier moves over the polishing pad. The refurbishing element is connected to the distal face of the body so that the refurbishing element can operatively engage the polishing surface substantially adjacent to the perimeter of the wafer carrier.

Abstract: A slot machine comprising display means (110) having a display screen provided on a plane opposed to a player, display control means (401) for controlling the display means (110) so as to display a still condition and a game play condition for each display window, start instruction means (108) for accepting a game play start instruction and instructing the display control means to start operation, stop instruction means (109) for accepting an instruction for stopping symbol change for each display window and instructing the display control means to stop operation, and game control means (403) for controlling game progress, wherein the improvement comprises storage means (904) for storing a plurality of symbol patterns and outputting the stored data to the display means based on read address specification, and background storage means (905) for storing backgrounds to be displayed on the display means, the display control (401) means issuing an output instruction to the storage means and the background storage

Abstract: The present invention provides for substituted metal chelating compounds in which at least two of the chelating atoms are nitrogen which are directly attached to aromatic rings and one or more of those nitrogen atoms has attached thereto a substituent other than hydrogen, and methods for making and using these compounds.

Abstract: In a packetized memory device, pipelined row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The column path also includes a set of bank address latches so that bank addresses can be pipelined synchronously with column addresses. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array. The bank address latches also activate a selected bank responsive to the strobe.

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs.

Abstract: An apparatus and method for accumulating specified weights of objects, such as apples, and delivering them to a plurality of off-load conveyors, the off-load conveyors delivering the apples to chutes which can then guide the apples into a single bagging apparatus. The flow of the apples on the chutes is controlled by a gate overlying all the chutes and a speed control brush that rotates at a desired speed to control the flow rate of the apples down the chute into the bagger. The apparatus and method are controlled by the interaction of a computer and a programmable logic controller.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:defining an isolation region on a layer of silicon oxide overlying a silicon layer;selectively etching the silicon to provide the isolation region;growing thermal oxide over the interior surfaces of the isolation structure;depositing dielectric conformingly; andoxidizing the deposited dielectric.

Abstract: A building having a plurality of floors, a plurality of detectors, such as smoke detectors, located on the floors, and an elevator system usable for moving building occupants between floors during an emergency condition, such as a building fire. The elevator system includes a control unit that controls movement of an elevator car between selected floors within an emergency evacuation zone for evacuation of building occupants to a designated evacuation assistance floor. The vertical movement of the elevator car is controlled relative to the detection of smoke within the building to increase the efficiency of emergency evacuation. The elevator and smoke detection systems are equipped with an emergency power source for operation in the event of a power outage. A signal control system receives status information from the building systems, including the elevator system, an air handling system, and a fire suppression system.

Abstract: A method and system for opportunistically downloading data from a server computer system to client computer systems. The server computer system has a point-to-point transmission mechanism for receiving data from each client computer system and has a broadcast transmission mechanism for broadcasting data to the client computer systems. Each client computer system has a broadcast receiver for receiving data broadcast by the broadcast transmission mechanism when the client computer system is in a receiving state. In a preferred embodiment, the server computer system selects data to be downloaded from the server computer system to the client computer systems, and broadcasts the selected data using the broadcast transmission mechanism. Each client computer system that is in the receiving state receives the broadcasted data and sends a confirmation that the client computer system has received the broadcasted data to the server computer system using the point-to-point transmission mechanism.

Abstract: A method and apparatus for operating a screw drive apparatus. The apparatus may include a threaded rod having a helical thread, a nut disposed about the threaded rod and having a load-bearing channel aligned with and radially outward from the helical thread, and a plurality of balls between the helical thread and the load-bearing channel. The apparatus may further include a housing with at least one support bearing having an inner race coupled to the nut and an outer race coupled to the housing and rotatable relative to the inner race. A retaining member is removably and adjustably coupled to the nut to apply an adjustable force against the support bearing in a direction generally parallel to a longitudinal axis of the threaded rod.

Abstract: A method and system for scheduling the use of a computer system resource using a resource planner and a resource provider is provided. In a preferred embodiment, a resource is scheduled for use by a plurality of consumer entities. Each consumer entity may request the commitment of a share of the resource. The method and system utilizes representations of resource usage policy, present commitments of shares of the resource, and present commitments of specified amounts of the resource over specified period of time. The method and system first receives a request from a consumer entity for the commitment of a specified share of the resource. In response, the method and system determines whether the specified share of the resource should be committed to the requesting consumer entity. This determination is based on the representations of resource usage policy and present commitments of shares of the resource.

Abstract: A computer system having a motherboard that is adapted to receive a daughterboard containing a CPU coupled to a PCI bus and a memory device through a system controller. The PCI bus is, in turn, coupled to a storage device, such as a programmable array logic device, containing CPU data identifying the type of CPU or other hardware installed on the daughterboard. The motherboard includes a memory device storing a BIOS program as well as a startup program. The startup program is executed by the CPU at power up or reset to cause the CPU to compare the CPU data identifying the CPU to BIOS data identifying the CPU adapted to execute the BIOS program. In the event that the CPU data and the BIOS data match, the CPU executes the BIOS program in a normal manner. In the event the CPU data does not match the BIOS data, the CPU executes a crisis recovery routine which may involve writing the proper BIOS program from a floppy disk to a programmable memory device containing the BIOS program on the motherboard.

Abstract: The present invention relates to a device for starting and supplying a fluorescent tube, including a resonant system connected to the tube and to a rectified supply circuit with a switch in series. A first detector controls the switch to turn off when the current provided by the supply exceeds a determined threshold; and a second detector controls the switch to turn on for each transition through zero of the voltage on a node of the resonant system and for each transition through a minimum of this voltage.

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed.

Abstract: Logon certificates are provided to support disconnected operation within the distributed system. Each logon certificate is a secure package holding credentials information sufficient to establish the identity and rights and privileges for a user/machine in a domain that is not their home domain. When a user/machine attempts to connect to the system at a domain other than the home domain of the user/machine, the user/machine presents a logon certificate that evidences his credentials. The domain where the user/machine attempts to connect to the system, decrypts and unseals the secure package as required to obtain the credentials information contained therein. If the user/machine has sufficient credentials, the user/machine is permitted to connect to the system. If the user/machine lacks sufficient credentials, the user/machine is not permitted to connect to the system.

Abstract: A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).