Patents Represented by Attorney Silicon Valley Patent Group
  • Patent number: 7808265
    Abstract: A circuit uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The circuit includes two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some embodiments, each stack includes a first-type device (e.g. a p-channel device) and at least two second-type devices (e.g. n-channel devices). The first-type device is used as a current source or as a select switch (depending on the mode of operation of the differential voltage defectivity monitoring circuit). One second-type device may be used as a select switch and for back-bias control, while another second-type device may be used as a blocking switch and/or a select switch. The circuit may be built into an addressable array of multiple test structures that have digitally multiplexed control lines, in some embodiments.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 5, 2010
    Assignee: SYNOPSYS, Inc.
    Inventors: John D. Garcia, II, Vipin P. Madangarli
  • Patent number: 7809763
    Abstract: Two computers are respectively programmed to generate descriptions of database objects (such as tables) in a first database, and compare the generated descriptions to corresponding schema objects in a second database. Objects in the second database are changed to conform to the first database if differences are found during comparison. The just-described differences in objects may arise due to changes being made to a software program that uses data contained in the objects.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: October 5, 2010
    Assignee: Oracle International Corporation
    Inventors: Sarita Brahmandam Nori, Christine Pae, Bhuvaneswari Thiagarajan
  • Patent number: 7808559
    Abstract: A method and system for accumulating stillness characteristics is presented. The method and system generates field stillness characteristics for a current pixel of a current field. The field stillness characteristic is accumulated with an accumulated stillness characteristic that corresponds to a pixel location of the current pixel. The accumulated stillness characteristic includes stillness information regarding previous pixels of previous fields in the same pixel location as the current pixel.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: October 5, 2010
    Assignee: Huaya Microelectronics, Inc
    Inventors: Ge Zhu, Edward Chen, Zhengjun Gong, Qing Yang
  • Patent number: 7807523
    Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. A multi step epitaxial process can be used to extend the ridges with different dopant types, high mobility semiconductor, and or advanced multi-layer strutures.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: October 5, 2010
    Assignee: SYNOPSYS, Inc.
    Inventors: Tsu Jae King Liu, Qiang Lu
  • Patent number: 7804662
    Abstract: In a perpendicular recording head, a notch is formed in the top write gap at a location on top of the main pole. A perpendicular head with this notched top write gap structure has less transition curvature and better writability while reducing the adjacent track interference (ATI). Also, the process used to fabricate the head ensures that the trailing edge (writing edge) of the main pole is extremely flat with no corner rounding.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: September 28, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tsung Yuan Chen, Hung-Chin Guthrie, Yimin Hsu, Ming Jiang
  • Patent number: 7804641
    Abstract: A method of automatically focusing a microscope in which a beam of light is directed from a light source through an objective of the microscope system to an object whereby light is reflected from the surface thereof; reflected light is collected and directed to an imaging system. The incident beam of light is limited in spatial extent by imaging an aperture to form an illumination pupil, the centroid of illumination of the illumination pupil is aligned with the incident optical axis of the instrument. The reflected light is split in the imaging system into at least one pair of images from eccentric sections of an imaging pupil displaced from the optical axis in opposite directions. The separation of the images thereby produced is determined to provide an indication of the object distance. A focusing system implementing the method and a microscope fitted with such a system are also described.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: September 28, 2010
    Assignee: Nanometrics Incorporated
    Inventors: Michael J. Hammond, Gregory T. Reynolds
  • Patent number: 7804544
    Abstract: A method and system for performing still pixel detection is presented. In accordance with the present invention, still pixel detection can use multiple thresholds and multiple windows of pixels. In a particular embodiment of the present invention, a still pixel detection test is performed using a first window. If the first window test determines the pixel is a still pixel then the pixel is classified as a still pixel. If the first window test determines the pixel is not a still pixel, a still pixel detection test is performed using a second window. If the second window test determines the pixel is a still pixel then the pixel is classified as a still pixel. Otherwise, the pixel is not classified as a still pixel. Some embodiment of the present invention the still pixel tests use multiple thresholds to determine if a pixel is a still pixel.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: September 28, 2010
    Assignee: Huaya Microelectronics, Ltd.
    Inventors: Ge Zhu, Edward Chen, Henry Haojan Tung
  • Patent number: 7795906
    Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: September 14, 2010
    Assignee: Synopsys, Inc.
    Inventor: Jamil Kawa
  • Patent number: 7797654
    Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 14, 2010
    Assignee: Synopsys, Inc.
    Inventors: Philip Hui-Yuh Tai, Yi-Min Jiang, Sung-Hoon Kwon
  • Patent number: 7793241
    Abstract: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ?V, in a matrix equation G?V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 7, 2010
    Assignee: SYNOPSYS, Inc.
    Inventors: Philip Hui-Yuh Tai, Yi-Min Jiang, Sung-Hoon Kwon
  • Patent number: 7761411
    Abstract: A computer modifies data inside a database large object (LOB) of unknown structure without modifying other data in the remainder of the LOB. Insertion of new data at a specified location in the LOB does not require movement of existing data in the LOB. Instead, the computer is programmed to insert new data at a physical end of the LOB, and modify metadata based on the specified location. Similarly, deletion of existing data from a specified location in the LOB is performed without movement of other data in the LOB, by updating the metadata. The computer uses the metadata when reading from the LOB, so that the new data is automatically read whenever the specified location is accessed. The computer may optionally output a handle that is static, relative to other insertions and deletions, to identify specific data within the LOB, for use in building indexes on the LOB.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: July 20, 2010
    Assignee: Oracle International Corporation
    Inventors: Shaoyu Wang, Amit Ganesh, Dheeraj Pandey
  • Patent number: 7751061
    Abstract: Non-contact apparatus and methods for evaluating at least one of the DC (or RF) dielectric constant, the hardness, and Young's Modulus of a dielectric material on a microelectronic workpiece under process and for generating a correlation factor that relates a measured IR spectrum to at least one of the dielectric constant, the hardness, and Young's Modulus of the dielectric material. A specific example of a method comprises measuring a thickness of the dielectric material on the process workpiece, irradiating the process workpiece with an IR source, and collecting and measuring an IR spectrum from the process workpiece. The measured thickness and at least a portion of the measured IR spectrum from the process workpiece are used with the correlation factor to determine at least one of the dielectric constant, the hardness, and Young's Modulus of the dielectric material. The determined value from the correlation factor is then stored and/or displayed.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: July 6, 2010
    Assignee: Nanometrics Incorporated
    Inventor: Pedro Vagos
  • Patent number: 7738565
    Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: June 15, 2010
    Assignee: Magnetic Recording Solutions, Inc.
    Inventors: Victor Pogrebinsky, Vladimir Pogrebinsky
  • Patent number: 7739265
    Abstract: A first continuous query is deleted from several continuous queries that are being executed, by performing different actions that depend on how resources are shared therebetween. As an example, a second continuous query is deleted if a view is referenced by the first continuous query, and if the view is built on the second continuous query, and if the view is not referenced by any query other than the first continuous query. Such deletion is followed by compiling the second continuous query, followed by updating the view to refer to a newly-compiled version of the second continuous query. As another example, if an operator in the first continuous query is not used by any other query, this operator is de-scheduled from execution, and any exclusively-owned resources are released. Also, data to be read by the operator and data generated by the operator, if present in shared resources, are deleted therefrom.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 15, 2010
    Assignee: Oracle International Corporation
    Inventors: Namit Jain, Anand Srinivasan, Shailendra Kumar Mishra
  • Patent number: 7734581
    Abstract: An array update operation which specifies number of (row-identifier, value) pairs for updating rows in a table of a database is implemented as follows. A block-identifier of a block (on disk) that holds a row identified by a row-identifier in a specified pair is looked up using a database index, and the block-identifier thus found is stored in a structure. Use of a row-identifier to look up the corresponding block-identifier, and the storage of the block-identifier in the structure are repeatedly performed, for each of several specified pairs. Next, a vector read is performed, to read and store in a cache, each block identified by a block-identifier in the structure, and all the blocks that have been read are stored in the cache during a single function call. Thereafter, rows identified in specified pairs are modified, in blocks currently in the cache, using the values in the specified pairs.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: June 8, 2010
    Assignee: Oracle International Corporation
    Inventors: Richard Yu Gu, Ashish Thusoo, Amit Ganesh
  • Patent number: 7722436
    Abstract: During planarization of wafers, the thickness of a layer of a wafer is measured at a number of locations, after the wafer has been planarized by chemical mechanical polishing. The thickness measurements are used to automatically determine, from a center to edge profile model to which the measurements are fit, a parameter that controls chemical mechanical polishing, called “backside pressure.” Backside pressure is determined in some embodiments by a logic test based on the center-to-edge profile model, coefficient of determination R-square of the model, and current value of backside pressure. Note that a “backside pressure” set point is adjusted only if the fit of the measurements to the model is good, e.g. as indicated by R-square being greater than a predetermined limit. Next, the backside pressure that has been determined from the model is used in planarizing a subsequent wafer.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: May 25, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hung-Chin Guthrie, Ming Jiang, Yeak-Chong Wong
  • Patent number: 7718134
    Abstract: A well plate and its supporting devices provide capabilities found in larger fermenters, such as controlling the oxygen level, the pH level, and temperature of the contents of the well. The well plate includes a plurality of wells, each of which can be independently controlled. Apertures in the wells, for example, provide access for a gas supply and sensors within each well provide data relating to, e.g., oxygen and/or pH level in the well. A control system controls the gas supply for each well based on the information provided by the sensor within the well. Similarly, temperature control elements, such as a heater or cooler, is placed in thermal contact with the interior of the well, as is a temperature measurement element. A control system can independently control the temperature of the contents of the well based on information provided by the temperature measurement element for that well.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 18, 2010
    Assignee: Microreactor Technologies, Inc.
    Inventors: David L. Klein, Stephen G. Boyer, Gregory Andronaco
  • Patent number: 7720301
    Abstract: A method and system for characterizing structures in an image are presented. The method and system generates a structure checksum value based on a plurality of pixels in the image. The structure checksum is used as an index of a look-up table containing structure characteristics corresponding to the structure checksum values.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: May 18, 2010
    Assignee: Huaya Microelectronics, Ltd.
    Inventor: Ge Zhu
  • Patent number: 7713404
    Abstract: An apparatus and method for improving the accuracy of Electrochemical Capacitance Voltage (ECV) profiling measurements by alerting the operator to the presence of surface films or gas bubbles during the etching process and by using this in-situ monitoring apparatus to determine the true measurement area at the end of the measurement cycle and using the new value to recalculate the data. By making the area measurement integral to the ECV tool, every sample measurement can be corrected for the true measurement area, leading to improved accuracy and eliminating a large source of error.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: May 11, 2010
    Assignee: Nanometrics Incorporated
    Inventors: Ian Mayes, Michael Sweeney, Harvey Podgorney, Clive Meaton
  • Patent number: 7713486
    Abstract: A well plate and its supporting devices provide capabilities found in larger fermenters, such as controlling the oxygen level, the pH level, and temperature of the contents of the well. The well plate includes a plurality of wells, each of which can be independently controlled. Apertures in the wells, for example, provide access for a gas supply and sensors within each well provide data relating to, e.g., oxygen and/or pH level in the well. A control system controls the gas supply for each well based on the information provided by the sensor within the well. Similarly, temperature control elements, such as a heater or cooler, is placed in thermal contact with the interior of the well, as is a temperature measurement element. A control system can independently control the temperature of the contents of the well based on information provided by the temperature measurement element for that well.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: May 11, 2010
    Assignee: Microreactor Technologies, Inc.
    Inventors: David L. Klein, Stephen G. Boyer, Gregory Andronaco