Abstract: One or more possibilities that are normally displayed in response to input from a user are augmented with real time information. Displaying real time information for one or more of the possibilities enables the user to take such information into account in deciding whether or not to continue with an action that the user was in the process of performing. For example, if a partial data entry provided by the user is indicative of an extension number to be dialed to place a phone call, and if a telephone call manager that receives the user's input displays call activity indicating that the user's intended callee is already on the phone, the user may decide to wait until the callee becomes available (as indicated by a change in callee's call activity).

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract: A computer is programmed to automatically generate repairs to fix failure(s) while taking into account dependencies between repairs relative to one another, by grouping failures. In some embodiments, the computer uses a map that associates each failure type with repair types that are alternatives to one another, and uses another map that associates each repair type with a template that creates the repair when instantiated. In certain embodiments, repairs within a repair plan are consolidated, to avoid duplicates and redundancies.

Abstract: A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constraints, on random values for signals to be input to the circuit during simulation of the design. Application of the rules identifies one or more templates of goal(s) to be met. The computer is programmed to automatically use constraint(s) and template(s) to instantiate goal(s) in memory. Each goal identifies a signal to be input to the circuit, and defines a counter for a value of the signal. The goals are used in the normal manner, i.e. used to measure coverage of functional verification during simulation of the design of the circuit.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated.

Abstract: A computer receives a schema that lacks information required by a directory access protocol (e.g. LDAP) and automatically generates information that conforms to the directory access protocol and supplies the generated information as output in a new schema. Such automatic schema transformation allows a human who is creating the schema, to enable usage of the directory access protocol to interface with a directory implementing the schema, without knowing the directory access protocol. The computer of some embodiments receives the schema being input, in a predetermined human-readable language (e.g. XML). Hence, an XML developer who lacks knowledge of LDAP can use traditional XML tools to prepare an LDAP-incompatible schema, for use in implementing a directory (e.g. address book) that is accessed by an LDAP client (e.g. cell phone) via an LDAP server. The new schema can be output in any form (e.g. text/binary) and in any language.

Abstract: Systems and methods are provided wherein an incoming plain old telephone systems (PSTN) signal is input into a network conversion interface. The network conversion interface first determines the data type of the incoming signal. Next, the network conversion interface creates a routing sequence of the incoming signal based on the determined data type. Finally, the network conversion interface converts the incoming signal into an 802.X format and sends the signal to an appropriate IP device based on the determined signal type. Should the network conversion interface lose electrical power, a drop contactor routes the incoming signal directly to an analog device without creating a routing sequence or performing an 802.X conversion.

Abstract: A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.

Abstract: In an application executing in multiple computers connected by a network, an instance of the application is deleted from a group of instances that share a resource, such as a database. Specifically the to-be-deleted instance is shut down, followed by deleting connectivity between the to-be-deleted instance and the network, and then deleting an object of the to-be-deleted instance. Each of these acts is performed automatically without user input, once the user issues an instruction to delete the to-be-deleted instance.

Abstract: In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.

Abstract: A method of fabricating a single-pole perpendicular magnetic recording head to contain a bevel angle promotion layer that facilitates the fabrication of the bevel angle in a trapezoidal main pole. The bevel angle promotion layer is made of a non-magnetic material that is softer than the material (e.g., Al2O3) that normally underlies the main pole. In one embodiment, the bevel angle promotion layer is formed between an end of the yoke and the air bearing surface (ABS), with the top surface of the bevel angle promotion layer being substantially coplanar with the top surface of the yoke. In other embodiment the bevel angle promotion layer is integrated with a leading edge taper material, which is formed of a magnetic material, to broaden the magnetic flux path between the yoke and the main pole.

Abstract: A sealing ring assembly and an improved method for mounting a sealing ring into an electrochemical cell used for Electrochemical Capacitance Voltage (ECV) profiling measurements. The ring is located in a holder having at least one secondary bore providing fluid communication between a forward face of the holder and the central bore of the ring, directed parallel to but tangentially offset relative to the inner wall of the central bore so as to impart a degree of rotational flow to electrolyte entering the sealing ring through the or each secondary bore which effectively removes gas bubbles and refreshes the electrolyte. The holder facilitates ring removal with a much reduced risk of damage to the delicate sealing surface.

Abstract: To implement pipelining, data from a first test written in a DBMS procedural language (such as PL/SQL) is automatically passed to a second test which may or may not be in the same language. A user creates a container test to identify names of the two tests, and adds one or more procedure(s) with predetermined name(s), to identify dependencies between the tests. In the first test, to supply data for the second test, the user includes one or more additional procedure(s) of predetermined name(s), to support an interface to a runtime data store. The second test reads data from the runtime data store. In certain embodiments, an adapter extracts test names from the container test and uses each name to create an object for each test, and during execution of methods in each object a database call is issued.

Abstract: Space on disk, designated for storage of recovery files is automatically managed so as to not exceed a predetermined limit. Specifically, after creation of information to be stored in a new recovery file, an automatic check is made to see if creation of the new recovery file will cause the space to exceed the limit. If so, at least one recovery file currently in the space is deleted. The new recovery file is automatically created, when the space occupied by existing recovery files becomes sufficiently small to accommodate the new file without exceeding the limit. The recovery file(s) deleted to make room for the new recovery file may be automatically identified in accordance with a user-specified policy. Such a policy may be used to automatically identify a subset of recovery files available for deletion, well ahead of time, i.e. prior to a need for deletion arises.

Abstract: A computer, for planning moves of freight automatically adds one or more layover(s) to a mission. Next, the computer determines one or more charge(s) for the layovers, using carriers' rules. Thereafter, the computer uses the charge(s) in deciding whether to include the mission in a transportation plan to be executed. In some embodiments, the computer automatically maintains, for the given mission, counts of attributes on which limits are imposed by a government or by carriers, such as driving time, on-duty time, and driving distance, and when any count exceeds a corresponding limit in the midst of a driving activity, the computer automatically divides up the current driving activity into a truncated driving activity and a remainder driving activity, separated by a layover activity. The computer also determines an estimated time of arrival, including the impact of required layovers, to reach destination(s), and whether layover(s) is/are required at the destination(s), e.g.

Abstract: A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around the sensitive spots. The sensitive spots are scored using a measure such as intensity (of light) or scoring based on contrast.

Abstract: In a computer simulation of an analog device in a digital circuit, a piece-wise linear lookup table is used to determine the channel resistance of the transistors in the analog device, allowing the node voltages to take on non-digital values. The piece-wise linear lookup table contains a set of channel resistances corresponding respectively to gate-to-source voltages. The program uses multi-terminal binary decision graphs (MTBDDs) to represent non-digital resistances, capacitances and voltages in the circuit as a function of symbolic inputs. The program can analyze circuits containing more than two voltage sources by modeling voltage sources with voltage dividers between the maximum and minimum voltages in the circuit.

Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

Abstract: Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined.