Abstract: A metal-to-metal conductive plug-type antifuise has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor.

Abstract: An optical measurement instrument that detects and analyzes reflected light includes a sample support, such as a wafer supporting chuck, with a sample bearing surface that is configured so as to not reflect light back to the optical measurement instrument. In one embodiment, the sample bearing surface of the sample support is a layer of material that absorbs light in the wavelength or wavelengths being used by the optical measurement instrument. For example, a hard plastic, such as poly-ether-ether-ketone (PEEK), may be used to absorb light in the infrared wavelengths. In another embodiment, the entire sample support may be manufactured from the light absorbing material. In yet another embodiment, the top surface of the sample support is configured with light scattering depressions, which prevent light that is incident on the sample bearing surface from being reflected back to the optical measurement instrument.

Abstract: A flat-panel display contains a pair of plate structures (40 and 42) coupled together to form a sealed enclosure. A spacer (44) is situated in the enclosure for resisting external forces exerted on the display. The spacer is formed with a main spacer portion (60), typically shaped like a wall, and a face electrode (66) situated over a face of the main spacer portion. The face electrode causes electrons moving from one of the plate structures to the other to be deflected in such a manner as to compensate for other electron deflection caused by the presence of the spacer. The face electrode is divided into multiple laterally separated segments (66.sub.1 -66.sub.N) to improve the accuracy of the compensation along the length of the spacer. In fabricating the display, a masking step is typically utilized in defining the widths of the segments of the face electrode.

Abstract: A semiconductor chip packaging method includes the provision of individual elastomer chip carriers cut from an elastomer sheet having a uniform thickness and smooth, parallel surfaces. The elastomer sheet is mounted on an adhesive tape held by a fixing member, such as a support ring, and is then divided into individual carriers. The carrier is attached to a circuit interposer, and a semiconductor chip is attached to the carrier. Circuit leads of the interposer are bonded to connection pads on the chip. The beam lead bonding area is then encapsulated, and conductive bumps are formed on the underside of the package to serve as input/output terminals for the packaged device. Using this method, an number of devices can be packaged simultaneously on a flexible sheet and then separated into individual devices by cutting the sheet between the devices.

Abstract: In a digital circuit, a method for avoiding a bus contention condition which results from an overlap of active phases of multiple bus drivers. The method avoids such bus contention condition by including holding amplifiers in the data bus and by turning on respective bus drivers only for durations sufficient to establish a data value on the data bus.

Abstract: A method for automatically generating a knowledge database in an object classification system having a digital image data source, and a computer, includes the steps of inputting digital image data corresponding to a plurality of training images, and characterizing the digital image data according to pre-defined variables, or descriptors, to thereby provide a plurality of descriptor vectors corresponding to the training images. Predetermined classification codes are inputted for the plurality of training images, to thereby define object class clusters comprising descriptor vector points having the same classification codes in N-dimensional Euclidean space. The descriptor vectors, or points, are reduced using a similarity matrix indicating proximity in N-dimensional Euclidean space, to select those descriptors vectors, called extreme points, which lie on the boundary surface of their respective class cluster. The non-selected points interior to the class cluster are not included in the knowledge database.

Abstract: An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections.

Abstract: Copolymers and terpolyers are used in chemically amplified resists. The terpolymers are of the formula: ##STR1## wherein R.sub.3 is selected from the group consisting of hydrogen and a C.sub.1 to C.sub.10 aliphatic hydrocarbon, wherein the aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof; R.sub.4 is selected from the group consisting of hydrogen and a C.sub.1 to C.sub.10 aliphatic hydrocarbon, wherein the aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof; R.sub.5 is selected from the group consisting of hydrogen and methyl; R.sub.6 is selected from the group consisting of t-butyl and tetrahydropyranyl; m and n are each integers; and wherein n/(m+n) ranges from about 0.1 to about 0.5.

Abstract: A method for nondestructive layer defect detection includes projecting radiation such as a laser beam on a surface of the layer. The surface of the layer is heated by the projected radiation so as to melt at least a portion of the layer. An impurity contained in a defect is heated by the projected radiation so as to increase the pressure of the material within the defect sufficiently to cause the impurity to emerge from the defect through the surface of the layer. The layer is then scanned for a visible defect created by the emergence of the impurity from the defect. A wafer scanning system for nondestructive layer defect detection includes a radiation source such as a laser and a wafer support system that supports a semiconductor wafer with a layer formed thereon in alignment with the radiation source.

Abstract: Apparatus for providing an optimized sampling phase to a received signal in a given channel, the received signal including inter-symbol interference. The apparatus includes a voltage controlled clock (VCC) for providing a VCC sampling phase, a first signal detector, connected to the VCC, for sampling the signal according to an advanced sampling phase which is advanced by a predetermined value .delta. with respect to the VCC sampling phase, thereby producing a first sampled signal, a second signal detector, connected to the VCC, for sampling the signal according to a delayed sampling phase which is delayed by a predetermined value .delta.

Abstract: An input buffer for use in an integrated circuit having a V.sub.CC voltage supply and a V.sub.SS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the V.sub.CC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the V.sub.SS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the V.sub.CC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: The invention herein describes a device for fabricating microarrays of biochemical substances, consisting of a holder and one or more printing pins. The holder contains apertures with regular spacing that define the location of one or more printing pins during the printing process. The tip of each printing pin contains a sample channel that holds a predetermined volume of biological or chemical sample and a point that is machined to precision with an electronic discharge machine (EDM). The device can be attached to a motion control system for precise and automated movement in three dimensions. The flat tips of the pins are immersed in a biochemical sample such that a predefined volume of sample fills the sample channel of each pin. The holder and pins are then moved in proximity to a printing substrate whereby direct contact between the flat tips of the pins and the surface results in the transfer of a small amount of the sample onto the solid surface.

Abstract: A linear motor, suitable to drive a photolithography positioning stage, incorporates a magnet array having transverse magnets and wedge magnets. The transverse magnets are spaced at regular intervals along a direction parallel with their magnetic polarities. Each transverse magnet is linked by a closed magnetic flux circuit with two adjacent wedge magnets having magnetic polarities oriented at an angle relative to the transverse magnet polarities. The local flux direction is substantially parallel to the magnetic polarity within each magnet, effectively enhancing magnetic flux density. Magnetic flux circuits are completed directly through the magnets and not through side rails, allowing selection of stronger, lighter-weight nonmagnetic side rail material. Wedge magnets with rectangular and trapezoidal cross-sectional shapes are described. Alternative array configurations contain two rows of complementary transverse and wedge magnets spaced on opposite sides of a coil array.

Abstract: A slurry dispenser dispensing slurry by a pair of counter-rotating wheels is provided in a chemical mechanical polishing process used in manufacturing integrated circuits. The slurry dispenser is driven by variable speed motors at a predetermined speed empirically determined to dispense a desired amount of slurry. The shape of the rotating wheels controls the vertical distribution of the spray. Openings in the housing of the slurry dispenser and the speed of rotation of the wheels controls the horizontal distribution of the spray. The slurry dispenser can be constructed out of materials chemically inert with respect to the slurry.

Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands.

Abstract: A method for optimizing layout design using logical and physical information performs placement, logic optimization and routing and routing estimates concurrently. In one embodiment, circuit elements of the integrated circuit is partitioned into clusters. The clusters are then placed and routed by iterating over an inner-loop and an outer-loop according to cost functions in the placement model which takes into consideration interconnect wiring delays. Iterating over the inner-loop, logic optimization steps improves the cost functions of the layout design. Iterating over the outer-loop, the size of the clusters, hence the granularity of the placement, is refined until the level of individual cells is reached. The present method is especially suited for parallel processing by multiple central processing units accessing a shared memory containing the design data base.

Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

Abstract: An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Abstract: A wavetable audio synthesis system includes a simplified burst data transmission interface and a modified wavetable data structure in a system memory to transfer wavetable data from the system memory to a wavetable audio synthesis device with reduced hardware complexity. The system memory is configured to store voice data in patches including a plurality of voice data samples beginning at an initial address and extending through a plurality of ramp voice data samples to a starting loop address. The voice data in the patches then includes a plurality of looping voice data samples from the starting loop address to an ending loop address. The voice data patches are extended by repeating the voice data samples beginning with the sample at the starting loop address and extending toward the samples at the ending loop address. The number of repeated samples extend for a number of samples equal to the size of a burst transfer.

Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.