Patents Represented by Attorney Slater & Matsil, L.L.P.
  • Patent number: 8279684
    Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Shun Chen, Cheng Hung Lee, Hong-Chen Cheng, Chung-Yi Wu
  • Patent number: 8279829
    Abstract: A network component comprising a processor configured to implement a method comprising receiving a multicast listening state (MLS) report comprising a multicast state data from a mobile node (MN), sending the multicast state data to an access router (AR), establishing a tunnel with the AR, and forwarding at least one multicast data stream associated with the multicast state data to the AR via the tunnel. Also disclosed is an AR configured to implement a method comprising receiving a multicast state data for a MN, evaluating the multicast state data, indicating whether the multicast state data is supported by the AR, establishing a tunnel with a second AR, and receiving at least one multicast data stream associated with the multicast state data from the second AR via the tunnel.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: October 2, 2012
    Assignee: FutureWei Technologies, Inc.
    Inventors: Yangsong Xia, Behcet Sarikaya
  • Patent number: 8275144
    Abstract: An intelligent audio speaker that uses a power line communication element to provide audio distribution within homes, businesses, apartment complexes, and other buildings. Multiple intelligent audio speakers may be networked together, with common control. The intelligent audio speaker may, in some embodiments of the present invention, contain enhanced ambient backlight effects to further enhance the listener's experience. In some embodiments of the present invention, an existing audio speaker is retrofitted to an intelligent audio speaker using a retrofit kit.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: September 25, 2012
    Assignee: STMicroelectronics, Inc.
    Inventors: Oleg Logvinov, Brion John Ebert
  • Patent number: 8274775
    Abstract: An electrical protection component with a short-circuiting device includes a surge arrester including at least two electrodes. The electrical protection component has at least one fusible element having a geometrical form including at least one cavity. A short-circuiting link is arranged at the surge arrester, wherein the short-circuiting link presses onto the fusible element. The short-circuiting link is spaced apart from the electrodes by means of the fusible element.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: September 25, 2012
    Assignee: EPCOS AG
    Inventor: Peter Bobert
  • Patent number: 8275584
    Abstract: A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Kai Lin, Cheng Hsiao, Sally Liu
  • Patent number: 8274657
    Abstract: A radiation detector is disclosed with a detector arrangement, which has a plurality of detector elements, by means of which a detector signal is obtained during operation of the radiation detector, and with a control device, wherein the detector elements each have a spectral sensitivity distribution, and are suited for generating signals, at least one detector element comprises a compound semiconductor material, and this detector element is designed for detecting radiation in the visible spectral region, the radiation detector is designed such that the sensitivity distributions of the detector elements are used to form different spectral sensitivity channels of the radiation detector, a channel signal assigned to the respective sensitivity channel can be generated in these sensitivity channels using the detector elements, and the control device is designed such that the contributions of different channel signals to the detector signal of the radiation detector are differently controlled.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 25, 2012
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Arndt Jaeger, Peter Stauss, Klaus Streubel, Werner Kuhlmann
  • Patent number: 8274071
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr.-Hung Li
  • Patent number: 8274343
    Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho
  • Patent number: 8274132
    Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: September 25, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Gunther Lehmann, Franz Ungar
  • Patent number: 8272876
    Abstract: Apparatus and methods for magnetically enhanced electrical signal conduction are disclosed. An embodiment electrical connector comprises a connector body, a first active signal contact mechanically attached to and at least partially disposed within the connector body, a ground contact mechanically attached to the connector body, an insulator mechanically separating and electrically isolating the first active signal contact and the ground contact, and a first permanent magnet electrically connected to the first active signal contact. An embodiment electrical cable comprises an elongated insulating sheath, a first active signal electrical conductor disposed within the sheath, a first connector body mechanically attached to a first end of the sheath, a first active signal contact mechanically attached to the first connector body, and electrically connected to the first active signal electrical conductor, and a first permanent magnet electrically connected to the first active signal electrical conductor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: September 25, 2012
    Assignee: Magnetic Innovations, L.L.C.
    Inventor: Ricky David Schultz
  • Patent number: 8275355
    Abstract: The present invention provides a method for a roaming user to establish security association with the application server in the visited network. When receiving the service request from the roaming user, the application server in the visited network establishes security association with the roaming user by making use of the authentication results of the generic authentication architecture in the home network via the BSF in the local network, or the generic authentication architecture proxy in the local network, or the AAA server in the local network and the AAA server in the roaming user's home network, so as to achieve the object that the roaming user is able to use the services of the visited network after authentication of the generic authentication architecture in his home network.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: September 25, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yingxin Huang, Wenlin Zhang
  • Patent number: 8273588
    Abstract: A method for producing a luminous device is specified. A number of light emitting diodes each have a radiation-transmissive carrier and at least two semiconductor bodies spatially separated from one another. Each semiconductor body is provided for generating electromagnetic radiation. The semiconductor bodies can be driven separately from one another and the semiconductor bodies are arranged at the top side of the radiation-transmissive carrier on the radiation-transmissive carrier. A chip assemblage is composed of CMOS chips each of which has at least two connection locations at its top side. At least one of the light emitting diodes is connected to one of the CMOS chips. The light emitting diode is arranged, at the top side of the radiation-transmissive carrier, at the top side of the CMOS chip and each semiconductor body of the light emitting diode is connected to a connection location of the CMOS chip.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: September 25, 2012
    Assignee: OSRAM Opto Semiconductros GmbH
    Inventors: Berthold Hahn, Markus Maute, Siegfried Herrmann
  • Patent number: 8274097
    Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Zhiyuan Cheng
  • Patent number: 8276110
    Abstract: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dinesh Baviskar, Wen-Hao Chen, Chung-Sheng Yuan, Mark Shane Peng, Yun-Han Lee
  • Patent number: 8274199
    Abstract: A piezoelectric multilayer component includes a stack of piezoceramic layers, which are arranged one on top of the other, and electrode layers. The stack has a first area and a second area. The second area contains a disturbance material, which is used to make the second area less mechanically robust than the first area.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 25, 2012
    Assignee: EPCOS AG
    Inventors: Georg Kuegerl, Oliver Dernovsek, Alexander Glazunov
  • Patent number: 8270977
    Abstract: A method for temporarily providing selected services by a base station cell of a communications system includes changing an operating mode of the cell in response to receiving a first command. The operating mode is indicated to a first selected device and a first non-selected device. The cell operating in the operating mode serves the first selected device based on the first command. The first non-selected device was a selected device and was capable of accessing the cell before the cell changed the operating mode. The first non-selected device is not capable of accessing the cell after the cell changed the operating mode.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: September 18, 2012
    Assignee: FutureWei Technologies, Inc.
    Inventor: Yunsong Yang
  • Patent number: 8269350
    Abstract: An interconnection component includes a plurality of through-substrate vias (TSVs) penetrating through a substrate. The plurality of TSVs includes an active TSV having a first end and a second end. The first end of the active TSV is electrically coupled to a signal-providing circuit. The second end of the active TSV is electrically coupled to an additional package component bonded to the interconnection component. The plurality of TSVs further includes a dummy TSV having a first end and a second end, wherein the first end is electrically coupled to the signal-providing circuit, and wherein the second end is open ended.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Chen, Chao-Yang Yeh, Meng-Lin Chung
  • Patent number: 8270131
    Abstract: An electrostatic discharge (ESD) protection element is described, the ESD protection element including a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: September 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Klein, Hans Taddiken, Winfried Bakalski
  • Patent number: 8268664
    Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: September 18, 2012
    Assignees: Altis Semiconductor, Adesto Technology Corporation
    Inventor: Faiz Dahmani
  • Patent number: RE43673
    Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen