Patents Represented by Attorney Slater & Matsil, L.L.P.

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  • Method, system, and device for transmitting TRAU frame over a packet network
    Patent number: 8295283
    Abstract: A method for transmitting a transcoder & rate adaptation unit (TRAU) frame over a packet network according to one embodiment of the present invention includes: receiving a packet TRAU (P_TRAU) frame sent from an opposite device; parsing the P_TRAU frame to obtain control information required for packet network transmission; and processing data in the P_TRAU frame according to the control information. A system and device for transmitting a TRAU frame over a packet network are also provided. With the P_TRAU frame that carries the control information required for packet network transmission, the Abis interface may use the packet mode instead of the time division multiplex (TDM) mode for transmission bearer and the delay, jitter, packet loss, and disorder in the packet mode are solved.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: October 23, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jinsong Hong
  • Semiconductor processing dispatch control
    Patent number: 8295965
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Process for adapting resonance frequency of a BAW resonator
    Patent number: 8291559
    Abstract: A method of manufacturing a filter circuit including series and parallel coupled BAW resonators is given which compensates for frequency tolerances of the resonators which are due to the manufacturing process. The new method includes measuring a resonance frequency of at least one type of the BAW resonators produced on a wafer and defining a deviation from a desired frequency. A trimming layer is then deposited onto the entire wafer. At last, a thickness portion of the trimming layer is selectively removed, the portion being dependent on a location on the wafer and on the calculated deviation of the resonance frequency at this location.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Epcos AG
    Inventors: Habbo Heinze, Edgar Schmidhammer, Monika Schmiedgen
  • System and method for non-uniform bit allocation in the quantization of channel state vectors
    Patent number: 8295379
    Abstract: A system and method for non-uniform bit allocation in the quantization of channel state vectors is provided. A method for communications node operation includes receiving a bit-allocation profile for use in quantizing channel state information, measuring a communications channel between the communications node and a controller, generating channel state information based on the measurement, computing a bit representation of the channel state information, transmitting the bit representation to the controller, and receiving a transmission from the controller. The computing makes use of quasi-tail-biting trellis decoding, and the computing is based on the bit-allocation policy. The transmission makes use of the channel state information transmitted by the communications node.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: October 23, 2012
    Assignee: FutureWei Technologies, Inc.
    Inventors: Chun Kin Au-Yeung, Shahab Sanayei
  • Semiconductor contact barrier
    Patent number: 8294274
    Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment includes a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Semiconductor device with thermal fault detection
    Patent number: 8296093
    Abstract: A semiconductor device includes a semiconductor chip including an active area. A temperature sensor arrangement provides a measurement signal dependent on the temperature in or close to the active area. An evaluation circuit is configured to compare the measurement signal with a first threshold and to signal an over-temperature when the measurement signal exceeds the first threshold. The evaluation circuit is also configured to count the number of exceedances of the first threshold and to signal when a maximum number of exceedances is reached.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: October 23, 2012
    Assignee: Infineon Technologies AG
    Inventors: Alberto Zanardi, Erich Scheikl, Robert Illing, Herbert Hopfgartner
  • Arrangement and method for measuring a current flowing in an electrical conductor
    Patent number: 8294452
    Abstract: An arrangement for measuring a current flowing in an electrical conductor includes a magnetic circuit, for coupling to the electrical conductor, the magnetic circuit has an air gap. A magnetic field-sensitive component that serves for measuring the magnetic field generated by the electrical conductor is situated between the arms of the magnetic circuit. Two control cores are arranged in the air gap of the magnetic circuit. The control cores each include a control winding for magnetically saturating the respective control core and are arranged on both sides of the electrical conductor.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 23, 2012
    Assignee: EPCOS AG
    Inventors: Bernhard Roellgen, Martin Neudecker
  • Method for increasing the ESD pulse stability of an electrical component
    Patent number: 8294547
    Abstract: A method for increasing the ESD pulse stability of an electrical component is disclosed. An electrical component is pre-aged by means of an aging pulse generated by a pulse generator. The degradation of an electrical characteristic curve of the component by ESD pulses that occur during operation of the electrical component is improved by the pre-aging.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 23, 2012
    Assignee: Epcos AG
    Inventors: Thomas Feichtinger, Markus Albrecher, Thomas Puerstinger, Guenter Engel
  • Radiate under-bump metallization structure for semiconductor devices
    Patent number: 8294264
    Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Wang, Chi-Chun Hsieh, An-Jhih Su, Hsien-Wei Chen, Shin-Puu Jeng, Liwei Lin
  • Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed
    Patent number: 8294212
    Abstract: Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Wei Wang, Chang-Ta Yang, Yuh-Jier Mii
  • Wireless connection method and device
    Patent number: 8295223
    Abstract: A wireless connection method is applicable to establishing a wireless connection device between an uplink device and a downlink device, and includes obtaining uplink wireless configuration information, and configuring a downlink with the obtained uplink wireless configuration information. A wireless connection is established with the uplink device based on the uplink wireless configuration information and, after successful connection establishment, a wireless connection is established with the downlink device based on the uplink wireless configuration information.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: October 23, 2012
    Assignee: Huawei Device Co., Ltd.
    Inventors: Jin Hua, Xujun Wang
  • Release accumulative charges on wafers using Oneutralization
    Patent number: 8293649
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 23, 2012
    Assignee: Global Unichip Corp.
    Inventors: Ting-Yi Lin, Chi-Yuan Wen
  • Wireless connection method and device
    Patent number: 8295222
    Abstract: A wireless connection method is applicable to establishing a wireless connection device between an uplink device and a downlink device, and includes obtaining uplink wireless configuration information, and configuring a downlink with the obtained uplink wireless configuration information. A wireless connection is established with the uplink device based on the uplink wireless configuration information and, after successful connection establishment, a wireless connection is established with the downlink device based on the uplink wireless configuration information.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Huawei Device Co., Ltd.
    Inventors: Jin Hua, Xujun Wang
  • Start-up circuits for starting up bandgap reference circuits
    Patent number: 8294450
    Abstract: An integrated circuit structure includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes a positive power supply node and a PMOS transistor including a source coupled to the positive power supply node. The start-up circuit is configured to be turned on during a start-up stage of the bandgap reference circuit, and to be turned off after the start-up stage. The start-up circuit includes a switch configured to interconnect a gate and a drain of the PMOS transistor during the start-up stage, and to disconnect the gate of the PMOS transistor from the drain of the PMOS transistor after the start-up stage.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Gu-Huan Li
  • Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors
    Patent number: 8294216
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Mong Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li
  • Package substrate
    Patent number: 8289727
    Abstract: In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: October 16, 2012
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., Global Unichip Corp.
    Inventors: Chin-Sung Lin, Li-Hua Lin, Yu-Yu Lin
  • Method and system for using logical resources
    Patent number: 8289915
    Abstract: The present invention discloses a method and system for using logical resources. The method includes: dividing a logical resource pool into at least one private resource pool and at least one shared resource pool, each of which matches one license that includes functions supported by the resource pool and/or capacity of the resource pool; enabling each private resource pool to be privately owned by one operator and each shared resource pool be shared by at least two operators; and using logical resources according to the license information. With the method and system of the present invention, it is easy to determine the apportionment rates of initial network construction costs and later expansion expenses and operators can expand capacity independently.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 16, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yun Wang
  • Method and apparatus for dynamic LMA assignment in proxy mobile IPv6 protocol
    Patent number: 8289862
    Abstract: Methods and apparatuses are provided for supporting mobility in a Proxy Mobile Internet Protocol (“IP”) network without having a mobile node (“MN”) to participate in certain mobility related signaling. Instead, a proxy agent might implement functions of a mobile access gateway (“MAG”) in a Proxy Mobile Internet Protocol Version 6 (“IPv6”) network. The proxy agent, rather than the MN, might send a request to a Dynamic Host Configuration Protocol (“DHCP”) server, and receive back a local mobility anchor address (“LMAA”) of a local mobility anchor (“LMA”). The proxy agent might instead perform a Domain Name System (“DNS”) lookup for the LMAA of the LMA first; in response to a failure to receive the LMAA, the proxy agent might then send the request to the DHCP server to receive the LMAA. The proxy agent might further update DNS information of the MN.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: October 16, 2012
    Assignee: FutureWei Technologies, Inc.
    Inventors: Yangsong Xia, Behcet Sarikaya
  • ESD protection structures on SOI substrates
    Patent number: 8288822
    Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
  • Vehicle protection system
    Patent number: 8286996
    Abstract: A system and method for protecting a vehicle and, more specifically, a truck bed is disclosed. A preferred embodiment comprises a system with three parts: a protective bar, one or more joint pieces attached to the protective bar, and one or more brackets attached to the one or more joint pieces. The brackets fit over the back end of the truck bed to hold the protective bar in place, while still keeping the overall system easily removable from the truck bed. Embodiments include both a single bracket as well as multiple brackets. The protective bar prevents cargo from impacting the front of the truck bed or back window while the cargo is being loaded, unloaded, or transported.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: October 16, 2012
    Inventor: Norman Grant