Abstract: A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

Abstract: A signal encoding method and device and a method for encoding a joint feedback signal are provided. The signal encoding method includes the following steps. When two carriers are configured with multiple-input and multiple-output (MIMO), Hybrid Automatic Repeat Request-Acknowledgement (HARQ-ACK) signals of the two carriers are combined into a joint feedback signal. The joint feedback signal is mapped into a codeword according to a predetermined mapping relationship between signals and codewords. Therefore, through the method for combining and encoding feedback signals of two carriers for transmission on a code channel in a dual cell (DC)-MIMO mode, bit error ratio (BER) and detection error cost are decreased, power overhead is saved, and a cubic metric (CM) value of the system is not affected, thereby enhancing the performance of the system.

Abstract: Methods for making a substrate for semiconductor packaging with improved warpage and an apparatus. A method includes providing on a die side of a substrate at least one flip chip mounted integrated circuit die. The substrate may include through substrate vias (TSVs). An underfill is dispensed between the integrated circuit die and the substrate. Initially the underfill is left uncured. A thermal interface material is provided on the upper surface of the at least one integrated circuit die. A heat sink is mounted over the integrated circuit die and in thermal contact with the thermal interface material. A thermal cure is performed to simultaneously cure the underfill material and the thermal interface material. In another embodiment, the thermal cure may simultaneously cure an adhesive mounting the heat sink to the substrate. Solder balls are disposed on a board surface of the substrate to form a ball grid array package.

Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.

Abstract: A lifting ring assembly includes a shackle plate, a shackle operably associated with the shackle plate, and a lifting ring operably associated with the shackle. The lifting ring assembly further includes a biasing element operably associated with the shackle plate and the lifting ring for biasing the lifting ring away from the shackle plate.

Abstract: An LED semiconductor body includes a number of at least two radiation-generating active layers. Each active layer has a forward voltage, wherein the number of active layers is adapted to an operating voltage in such a way that the voltage dropped across a series resistor connected in series with the active layers is at most of the same magnitude as a voltage dropped across the LED semiconductor body. The invention furthermore describes various uses of the LED semiconductor body.

Abstract: A power converter and method of controlling a power switch therein to improve power conversion efficiency at low output current. In one embodiment, the power converter includes a first power switch coupled to a source of electrical power and a second power switch coupled to the first power switch and to an output terminal of the power converter. The power converter also includes a controller configured to alternately enable conduction of the first and the second power switches with a duty cycle in response to an output characteristic of the power converter. The controller is configured to control a level of current in the first power switch when the second power switch is substantially disabled to conduct.

Abstract: A method for secure and reliable authentication in a communication system. In an embodiment, the authentication method includes performing authentication of a user utilizing Extensible Authentication Protocol (EAP), and transmitting a result indication message to the user. The result indication message can include additional information for security and reliability. The method also includes receiving an acknowledgement message from the user. The acknowledgement message is sent by the user for confirming the reception of the result indication. In an embodiment, the method also includes retransmitting the result indication message if the acknowledgement message is not received within a predetermined time. The additional information for security and reliability can include Message Authentication Code (MAC) and time interval information. The additional information for security and reliability can also include a security/reliability flag.

Abstract: A method for producing a ceramic material is disclosed. A ceramic raw material mixture is produced by comminuting and mixing starting materials containing Pb, Zr, Ti, Nd and oxygen. Nickel or an nickel compound is introduced. The raw material mixture is calcined and a ceramic is sintered.

Abstract: Guided bulk acoustic wave devices and method for manufacturing guided bulk acoustic wave devices are provided. A guided bulk acoustic wave device includes a resonator structure with a piezoelectric layer, an electrode layer for exciting guided bulk acoustic waves and a wave guide layer. The thickness of the piezoelectric layer is less than or equal to 50 ?m.

Abstract: A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.

Abstract: A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and have a repeated pattern.

Abstract: In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage.

Abstract: A circuit arrangement includes a first light emitting diode and a second light emitting diode emitting light of different colors arranged adjacent to each other for additive color mixing. A first and second controllable current sources are connected to the first and second light emitting diode, respectively, such that the load currents of the light emitting diodes depend on respective control signals received by the current sources. First and second sigma-delta modulators are connected to the first and second light emitting diodes, respectively, and provide bit-streams as control signals to the current sources. The mean value of each bit-stream corresponds to the value of an input signal of the respective sigma-delta modulator.

Abstract: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.

Abstract: System and method for generating a sense amplifier enable (“SAE”) signal having a programmable delay with a feedback loop to control the SAE signal duty cycle, which can be used in SRAM or DRAM, or other kinds of memory cells. An illustrative non-limiting embodiment comprises: a programmable clock chopper, a low pass filter, a bias generator, a comparator, and a feedback control module.

Abstract: A method of matching the power of a photovoltaic system producing electric energy by which a working point at which the system produces maximum power is set by changing the working point in an MPP matching process and by comparing the system power, which changes as a result thereof, is intended to be suited both for stationary characteristic curves and for non stationary generator characteristic curves and to be easy to carry out so that the best working point is always set, even when the system is subjected to external interfering factors. This is achieved in that one or several additional control steps or control cycles are performed in order to track during the matching process a power point changing under external impact for a working point of even higher power to be set.