Abstract: The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate.

Abstract: A transistor (14) having a plurality of sub-transistors (29a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.