Abstract: A memory cell is disclosed which operates in two stable states and where an asymmetry in current through the cell is required to change the state of the cell. The cell includes a current compensating device that supplies current under ionizing radiation in a direction that is opposite to that required to write into the cell.

Abstract: A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Abstract: A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor.

Abstract: A common-mode feedback circuit comprises a reference generator (12) for generating a signal corresponding to a desired common-mode operating point connected to a common-mode bias circuit (14) for generating a second signal corresponding to the common-mode operating point of the outputs (V.sub.out.sup.+, V.sub.out.sup.-) of the fully differential operational amplifier. In the preferred embodiment, the common-mode bias circuit (14) includes a sensing circuit (58) comprising two MOS transistors (60, 62) having sources and drains connected together. The MOS transistors (60, 62) operate in the ohmic region to provide a variable load responsive to the output signals (V.sub.out.sup.+, V.sub.out.sup.-) connected to their gates.

Abstract: A bit line latch sense amp is disclosed which substantially eliminates a number of problems associated with prior art sensing schemes which result through asymmetrical operation proximately caused by the use of separate bit line and separate sense amplifier pre-charge circuitry. The invention disclosed herein precharges the sense amplifier and its associated bit line at substantially the same time and does not require separate precharge circuitry for doing so.

Abstract: The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate.

Abstract: The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

Abstract: Single event upset hardening is provided in a static random access memory cell, including cross-coupled inverters, by the restoration of voltages at selected nodes within the cell by a pair of transistors connected to the cross-coupling between inverters.

Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).

Abstract: Method of forming an antireflective coating on a face of a semiconductor which includes forming a metal oxide layer on the face, heating the oxide layer to a temperature sufficiently high to cause the migration of free metal atoms over the surface of the metal oxide and then sputtering a thin layer of aluminum or aluminum alloy on the oxide layer of a thickness such that bumps are formed which reduce the specularity of the surface. The aluminum atoms form bumps which reduce the specularity of the surface.

Abstract: An A/D converter utilizing a charge redistribution scheme includes a single ended comparator and associated therewith a capacitor array of binary weighted capacitors. The input signal is sampled with the input of the comparator disposed at a point midway between ground and a unipolar reference voltage. The bottom plates of the capacitors in the hold mode are then disposed at the midpoint of the reference signal. In the redistribution mode, the value of the bits is determined by switching the bottom plates of the capacitors between the midpoint of the reference voltage and either ground or the full value of the reference voltage. The input signal during sampling is attenuated by sampling it onto only one-half of the array.

Abstract: A pass circuit (54) passes a boot signal through a first transistor (60) when the pass circuit (54) is selected by a select signal (106). A second transistor (100) is precharged prior to receiving the select signal (106). In response to the select signal (106), a high voltage is passed to the first transistor (60) and the voltage at the gate of the second transistor (100) is pulled above a high voltage. After a delay period, another transistor (88) conducts between the gate of the second transistor (100) and V.sub.cc, to discharge the gate voltage. With both the source and gate of the second transistor (100) at a high voltage, the second transistor (100) is put in a non-conducting state. As the boot signal passes through the first transistor (60), the gate voltage of the first transistor (60) is increased above a high voltage, but the voltage at the gate of the second transistor (100) is maintained at V.sub.CC, thus preventing junction breakdown.

Abstract: A water soluble contrast enhancement compound and composition, and a method of use thereof, are disclosed for improving sidewall profiles in photoresist patterning and developing. The compound consists of a 1-oxy-2-diazonaphthalene sulfonamide salt.

Abstract: A circuit is disclosed for generating a two-stage boot signal, the first stage being a transition from a low voltage to a high voltage, and the second stage being a transition from the high voltage to an increased high voltage. The first stage operates to read the contents from a memory cell, and the second stage operates to restore the contents of the access memory cell. A capacitor (102) is charged with a voltage to boost the output (122) of the circuit (52) in order to produce the increased high voltage. However, the lower plate (100) of the capacitor (102) is effectively disconnected from the circuit during the transition from a low to high voltage in order to provide a fast transition period.

Abstract: A low-power, noise-resistant, read-only memory (10) is comprised of a plurality of array sections (14), each section (14) having a plurality of cell locations (70-86) arranged in rows (98) and columns (88-96). Each column (88-96) is provided with a virtual ground line (107-114). Bit lines (116-126) are shared between columns (88-96). In operation, the bit lines (116-126) and virtual ground lines (107-114) are pulled up to a high voltage state. Then, one selected virtual ground line (107-114) in each section (14) is pulled low to address a pair of cell locations (70, 72) in that section (14). No active pullup means are employed. The transmission of false data through a sneak path (550) is prevented by the actuation of disconnect circuitry (38) after allowing all valid data to be sensed.

Abstract: An A/D converter includes a positive array of binary weighted capacitors with a common top plate (12) and a negative array of binary weighted capacitors with a common top plate (32). The positive and negative arrays are input to a differential amplifier (10) for measuring the differential voltage across the top plates. During the sample time, a differential input voltage is sampled on the bottom plates of the capacitors and the top plates of the capacitors are disposed at the common mode voltage of the input signal. This limits the input voltage across the capacitors to one-half the differential voltages of the input signal. During the hold mode and the redistribution mode, this presents a predetermined common mode input voltage to the amplifier (10) which is independent of the input signal.

Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Abstract: A combination inverter chain and ring oscillator (200) is used to measure the capacitance of a field effect transistor device (12, 85, 202) by measuring the current associated with propagating a signal through the circuit at a certain signal frequency. Where the device (12) is a CMOS pair, the capacitance thus obtained is reduced by a constant factor to take crowbar current (52) into account. Once the capacitance for a basic or reference device (84) has been determined, the basic structure may be modified to derive incremental per-unit area capacitances for various components of the device structure.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resistive circuitry which allow bootstrapped voltages.

Abstract: A dual dielectric gate system utilizes a dual dielectric system with a first silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The substrate is of silicon optionally counterdoped with germanium. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200 .ANG. to 1000 .ANG. (or greater). A layer of undoped amorphous silicon and a second layer of silicon dioxide, respectively overlie the first layer silicon dioxide, and an aluminum gate metal layer overlies the second silicon dioxide layer. The structure can be patterned by selectively patterning photoresist and a dry or a dry/wet etch processes. The structure is patterned and etched as desired.