Abstract: A plasma source for generating a plasma in a chamber in conjunction with a radio frequency generator is described. The plasma source comprises a coil spiral, at least one insulator and at least one capacitor. The coil spiral conducts the radio frequency wave from the radio frequency generator and induces a plasma in the chamber. It comprises at least two segments. Each insulator and capacitor couple two adjacent segments of the coil spiral together.

Abstract: A method of reticle fabrication is disclosed which will reduce e-beam write time by two orders of magnitude for a 64 megabit DRAM. The method involves the mix of using both e-beam and optical lithography on a single reticle.

Abstract: The distance between a semiconductor wafer and a bake/chill plate is determined by a feed back system using a flow meter. The wafer forms part of the feed back system by limiting the flow of air or gas between the wafer and bake/chill plate, the distance between the wafer and bake/chill plate determining the amount of flow of air or gas through the flow meter.

Abstract: A method and apparatus are provided for bidirectional current conduction between first and second nodes of an electronic circuit. A first substantially constant current is conducted through a first current mirror pair of transistors coupled between the first and second nodes, in a first direction away from the first node toward the second node, in response to the first node having a voltage higher than the second node. A second substantially constant current is conducted through a second current mirror pair of transistors coupled between the first and second nodes, in a second direction away from the second node toward the first node, in response to the first node having a voltage lower than the second node.

Abstract: In a method and circuitry for variable single transition counting, a count signal (178) is provided on a count line. A direction control bit (264) is output on a direction control line. A significant bit (278e) is output on a significant bit line. A first single transition count (278a-d) is incremented in response to the count signal (178) and to the direction control bit (264) having an incrementing logic state. The first single transition count (278a-d) is decremented in response to the count signal (178) and to the direction control bit (264) having a decrementing logic state. The first single transition count (278a-d) and the significant bit (278e) together form a second single transition count (278a-e). The second single transition count (278a-e) is compared against a preselected value (296), and a comparison signal (320) is output in response to the second single transition count (278a-e) being equal to the preselected value (296 ).

Abstract: A lead conditioning system (10) provides an offset conditioner (12), a planarity conditioner (14) and a tweeze conditioner station (16), a centering station (18), a transport assembly (20), a cabinet (22) having an input station (24) and an output station (26), and a control electronic control apparatus (28). Offset conditioner (12) conditions the offset spacing between leads of a gull-wing semiconductor device by shifting the leads axially in both directions and returning the leads to a center position according to a predetermined specification. Likewise, planarity conditioner station (14) deforms the leads of the semiconductor device so that the leads are essentially upright then repositions the leads by exerting forces downwardly on the tips of the leads so that the tips of the leads of the semiconductor device are essentially shifted to a coplanar position according to a predetermined specification.

Abstract: A single camera container inspection system that views the entire interior surface of a container during one pass, producing a single image of the interior surfaces to detect defects and contaminants in the interior surfaces of the container.

Abstract: An in-situ deep-ultraviolet light generation module (126) for photon-assisted processing of semiconductor wafers (44) comprises a process environment space (152) for photochemical processing applications. Process gas injection space (182) receives reactive process gases and injects them into process environment space (152). Plasma fill space (124) receives a plasma (120) and may direct plasma (120) away from or into the process environment space (152) according to the presence or absence of control gas (160) flow. Control gas space (174) and flow/pressure switch space (154) receive control gas (160) to selectively permit deep-ultraviolet photons or plasma to reach process environment space (152) and interact with wafer (44) for photo-enhanced or plasma-enhanced wafer processing.

Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.

Abstract: A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Abstract: A multiple compound CMOS domino circuit (234) is disclosed having a first input section (248) connected to a preliminary dynamic output node (244). A second input section (250) is connected to a preliminary output dynamic node (246) which is independent of the first dynamic node (244). Separate precharge devices (236, 238) precharge the respective dynamic nodes (244, 246) to a desired voltage. Separate discharge transistors (240, 242) operate in conjunction with the respective input sections (248, 250) to discharge the dynamic nodes (244, 246). Static output logic gates (252, 254) include inputs connected to the dynamic nodes (244, 246) and provide multiple outputs of the compound domino logic circuit (234).

Abstract: A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

Abstract: A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially perpendicular to the substrate surface between the surface and the capacitor. The capacitor comprises a storage layer which can be formed of a ferroelectric material such that the memory cell is nonvolatile. The storage layer may also comprise a high dielectric material such that the memory cell is operable as a dynamic random access memory cell.

Abstract: A multipurpose low-thermal-mass radio-frequency chuck for semiconductor device processing equipment (18) and applicable to plasma processing over a wide range of substrate temperatures. The stacked multilayer chuck structure comprises process vacuum base plate (16), heating module (48), cooling module (44) and radio-frequency power plate (50). Vacuum base plate (16) provides mechanical support and necessary feed-throughs (RF power connection, coolant inlet/outlet, heater wires and thermocouple) for main chuck (20). Water-cooled vacuum base plate (16) is thermally insulated from main chuck module (20). Heating element (48) comprises top layer (80) of electrical insulation and passivation, power heating resister (82), bottom layer of electrical insulation (84) and heater substrate (86) made of boron nitride or quartz or SiC-coated graphite.

Abstract: In one embodiment, a system for measuring the temperature of a first object, such as wafer 112, in the presence of a second radiating object, such as a heating lamp 118, is disclosed herein. A heating lamp 118 is provided for heating the wafer 112 for device processing. Both the wafer 112 and the lamp 118 emit radiation. A first detector 120 detects radiation emitted by both the wafer 112 and the lamp 118. A second detector 122 which detects radiation from only the heating lamp 118 may also be used. A modulation source 126 is provided for modulating the heater 118 to a selected modulation depth M.sub.L such that the temperature of the lamp 118 varies with the selected AC modulation and the temperature of the wafer 112 remains substantially constant. Also, circuitry is provided for determining the fraction of radiation emitted by the lamp and collected by the first detector 120 (lamp interference signal) based upon the heating lamp modulation and then calculating the precise temperature of the wafer 112.

Abstract: A gas distribution system 140 includes a gas distribution chamber 142 and a gas distributor 154. Gas distribution chamber 142 includes an open end 144 and a closed end 146. A workpiece 148 is disposed adjacent closed end 146. Gas distributor 154 includes an outer collar 156 and an inner collar 158. Inner collar 158 has a continuously increasing cross-sectional diameter from a first predetermined point 160 to a second predetermined point 162. Gases are introduced through an inlet tube 150 disposed through an aperture in a platform 152 into the interior of inner collar 158 and toward workpiece 148. A diverter 164 diverts incoming gases from inlet tube 150.

Abstract: BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

Abstract: A TiSi.sub.2 LI process solves the problems of poor junction integrity and rapid dopant outdiffusion by adding a second titanium deposition on the amorphous silicon/titanium stack and reducing the initial titanium thickness to its minimum required value for amorphous silicon etch stop. Referring to FIG. 5 of the drawings, titanium layer 60 reacts at exterior surface 58 of sidewall oxide 59 to form TiN layer 57. Layer 57 acts to stop outdiffusion of silicon into the second titanium layer 60. This second titanium deposition on the amorphous silicon/titanium stack minimizes differential TiSi.sub.2 formations because the silicon selected in TiSi.sub.2 formation originates from amorphous silicon layer 54, rather than from the source region 22 or drain region 23, resulting in better junction integrity. This process saves up to 25% of the area otherwise required in contacts for SRAMS, yielding much improved packing density.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: A memory device having an array of memory cells each including a trench capacitor and a pass transistor. The transistor has its source connected to the storage capacitor, its drain connected to a bit line, and its gate connected to a word line. The bit line is formed over a field oxide layer formed on the semiconductor substrate so there is minimal contact between the bit line and the semiconductor substrate. The storage dielectric in the trench is recessed from the surface of the semiconductor substrate.