Abstract: A threshold control BiCMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.

Abstract: A bias current supply circuit (20) is provided which includes an initial current source comprising a FET (22) coupled to a current mirror circuit comprising a pair of BJTs (26 and 28). An active resistive element comprising a second FET (24) is included to stabilize an output current I.sub.0 with respect to ambient temperature variations and process variations.

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

Abstract: A memory cell is disclosed comprising cross-coupled inverters including gated diodes connected in the cross-coupling which increase the memory cell's resistance to single event upset. The layouts for constructing such a memory cell, which optimize READ and WRITE speeds, are also disclosed.

Abstract: A non-volatile cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines from the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

Abstract: A memory cell which includes a pair of cross-coupled CMOS inverters. Each inverter has a capacitor coupled from its output to either the supply voltage or ground potential. One inverter has a capacitor coupled from its output to a voltage supply terminal and the other inverter has a capacitor coupled from its output to a ground terminal. Upon the application of power to the memory cell, the output of each inverter of the pair assumes a predetermined logic state thereby preventing dc current flow in either side of the cross coupled pair. In addition to providing for reduced power consumption, the selective cell assymetry provided makes possible a random access memory device that stores a fixed program at power up.

Abstract: A BiCMOS current source reference network which eliminates the impact of d.c. power supply voltage drops on the operation of ECL circuits is described. This invention is essential for implementing ECL design techniques in VLSI BiCMOS circuits. Using the current source network, reference voltages are generated locally so that the ECL voltage references are correctly referenced to the local power supply potentials. A power supply insensitive band-gap reference generator is used to generate precision on-chip voltage references and current sources. The band-gap circuit uses both MOS and bipolar transistors and is much simpler than a similar using bipolar-only circuitry.

Abstract: Asymmetrical delay circuitry comprising a chain of inverters connected to logic gates is disclosed which can be implemented at the word line driver or in the address decode circuitry of a memory.

Abstract: A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: An electrically erasable, programmable read only memory (EEPROM) having an erase window directly overlying both a control gate layer (24) and a column line (12) is disclosed. Column lines (12) are implanted into a semiconductor substrate (16) and covered with a first insulating layer (18). A floating gate layer (20) overlies the first insulating layer (18) and is covered with a second insulating layer (22). The control gate layer (24) overlies the control insulating layer (22) and is covered by a third insulating layer (26). A passage (28) extends through the third insulating layer (26), control gate layer (24) and second insulating layer (22) and contains a sidewall insulator (30) on walls thereof. A tunnel oxide (32) resides within the passage (28) and is contacted by a programming electrode layer (34) which additionally overlies the third insulating layer (26) and fills the passage (28).

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Abstract: A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: A bias current supply circuit (20) is provided which includes an initial current source comprising a FET (22) coupled to a current mirror circuit comprising a pair of BJTs (26 and 28). An active resistive element comprising a second FET (24) is included to stabilize an output current I.sub.O with respect to ambient temperature variations and process variations.

Abstract: An output driver circuit for reducing output terminal ringing in integrated circuits has a plurality of pull-down transistors each having first, second and third terminals. A plurality of voltage setting devices each are connected in series to the second terminal of one of the pull-down transistors. An input is connected to the common third terminals of the plurality of pull-down transistors, and an output pull-up circuit is connected between the output of the circuit and the first terminals of the plurality of pull-down transistors. Multiple output driver circuits, each having an input delayed with respect to the others, can be connected together with a common output.

Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

Abstract: A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Abstract: The rate of single event upset in a memory cell due to energetic particle hits on a p-channel device is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly. Additionally, means such as a resistor or transistor are disclosed which reduce the rate of single event upset due to energetic particle hits on a n-channel device.