Abstract: Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.

Abstract: A memory cell system with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. Data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.

Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the capacitor dielectric is deposited thereover. A first metal layer, such as titanium nitride or a titanium-tungsten alloy, is formed over the capacitor dielectric, and is patterned and etched to define the top plate of the capacitor and, accordingly, the capacitor size. Multilevel dielectric is formed thereover, and a contact via to the top plate is etched therethrough. Metallization is sputtered overall, to make contact to the top plate and elsewhere in the circuit.

Abstract: A semiconductor wafer (26) may have all the integrated circuits (36) formed thereon simultaneously self-tested by the addition of a power circuit, a ground circuit and clock circuit. Lead lines are formed during metallization of the integrated circuits (36) on the wafer (26). The lead lines are interconnected to the integrated circuits (36) to form a power input, a ground input and a clock input on each integrated circuit (36). A test head (28) having a power probe (44), a ground probe (46) and clock probe (48) is attached to the power, ground and clock circuits on the semiconductor wafer (36). The integrated circuits (36) are simultaneously tested by the test head (28), and failed circuits are identified by an infrared detector (42).

Abstract: A method and apparatus for measuring node voltage on an integrated circuit is diclosed herein. A sensing needle 10, which is connected to supply voltage 20, is positioned directly above node 12 on integrated circuit 14. Tunneling or field emission current 30 is produced in sensing needle 10 due to the difference in potential between sensing needle 10 and node 12. Supply voltage 20 is adjusted to set current 30 to an initial value. When the voltage on node 12 changes, the current 30 will also try to change. When a change in current 30 is detected, a signal 28 is generated to adjust supply voltage 20 such that current 30 returns to its initial value. Consequently, the change in supply voltage 20 mirrors the change in voltage on node 12.

Abstract: An electrically, programmable read-only memory cell is formed at a face (10) of a semiconductor layer (12). This cell comprises a doped drain region (36) and a doped source region (38) that are spaced from each other by a gate region (40). An ONO memory stack (28) is formed to extend over a portion of the gate region (40) that adjoins the drain region (36). The memory stack (28) is substantially spaced from the source region (38). A select gate insulator layer (30) is formed over the remainder of the gate region (40), and is preferably of the same thickness as the memory stack (28). A suitable gate conductor (32) is then deposited over insulator layers (26, 30). By being substantially spaced from source region (38), the memory stack (28) of the invention avoids the formation of ONO hole traps.

Abstract: A method of forming an integrated-circuit device (10) which provides increased packing of unrelated conductors such as first gate (14) and second gate (16). Strap (20) electrically connects conductor contact area (28) to moat contact area (30) and yet also overlies and overlaps gate (16) above the overlap area (27) without any danger of shorting first gate (14) to second gate (16). According to the invention, the possibility of shorting strap (20) to second gate (16) and hence first gate (14) to second gate (16), is eliminated in the processing sequence wherein second insulating layer (24) is patterned to expose conductor contact area (28) at a prior step in the processing sequence. Subsequently, a third insulating layer (26) is formed to re-cover conductor contact area (28), yet the thickness of third insulating layer (26) is substantially less than the combination of the thickness of third insulating layer (26) and second insulating layer (24).

Abstract: This invention discloses a method for reducing hot carriers in a transistor structure by means of increasing the scattering rate of the carriers. The increased scattering rate is accomplished by introducing scattering sites comprising of non-conventional dopants, an element which is not boron, phosphorous, or arsenic, into the base or channel region of a transistor.

Abstract: A method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30 . Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

Abstract: The described embodiments of the present invention provide a bipolar transistor using an integrated field effect load device with one end of the load device integrally formed with the base of the transistor. The gate of the load device is connected to the emitter of the transistor. This structure is particularly advantageous in bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuitry. The unconnected end of the load device may be connected to the emitter using standard metal interconnection techniques or local interconnection techniques. In an additional embodiment of the invention, the end of the load device not connected to the base may be left unisolated to the substrate and thus connected to ground. It often occurs that the emitter of the bipolar transistor will be connected to ground and thus an automatic connection of the load device between the base and the emitter can be realized.

Abstract: A process for selectively depositing a contacting material (20) in trenches (18) for a via or contact which selectively eliminates potential metal contaminants (22) by removing a sacrificial layer (16) after the material (20) is selectively deposited. Initially, the trenches (18) are formed by selectively exposing the substrate (10) to an etchant (19). After metal material (20) is deposited into the formed trenches (18), a chemical etchant (24) is used to remove the sacrificial layer (16) and any formed contaminants (22).

Abstract: A method for forming a quantum effect switching device is disclosed which comprises the step of forming a heterostructure substrate 10. A silicon nitride layer 22 is formed on an outer surface of the substrate 10. An aluminum mask body 30 is formed using a lift-off procedure. Aluminum mask body 30 is then used to form a silicon nitride mask body 32 from the silicon nitride layer 22 using a CF.sub.4 /O.sub.2 reactive ion etch process. A boron trichloride etch process is then used to form a dual column structure 34 while removing the aluminum mask body 30. A buffered HF wet etch process removes the silicon nitride mask body 32. Separate metal contacts can then be made to electrically separate points on the outer surface of the dual column structure 34.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A BiCMOS static random access memory is disclosed, where the sense amplifiers each consist of a pair of bipolar transistors connected in emitter-coupled fashion. A pair of current sources, such as MOS transistors, are connected between the bases of said bipolar transistors and ground, to provide additional pull-down current for the bit lines. This additional pull-down current reduces the differential bit line voltage, improving the speed at which subsequent reads may be performed. Another embodiment uses a dummy column as a detection circuit, with the output of the dummy column controlling an operational amplifier, so that the operational amplifier may bias the current source pair to control the pull-down current, and thus the differential bit line voltage. Another embodiment controls the current source pair responsive to the row address, so that the effects of series bit line resistance may be taken into account in establishing the desired pull-down current.

Abstract: A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.

Abstract: This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g.

Abstract: A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).