Abstract: A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.

Abstract: An example of a solution provided here comprises receiving project-characteristic inputs for a project, receiving major-services inputs for the project, applying analysis rules to the inputs, and outputting, for the project, at least one complexity measure that is usable in an estimation process.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: Mechanisms for creating global sessions across different protocols and multiple converged protocol applications are provided. By creating a global session, state information for each of the individual protocol sessions may be communicated across protocols and utilized in performing operations across converged protocol applications. An edge server is used at the edge of a data network to correlate client interactions over different protocols and to associate them with a global session. The edge server acts as a session reference counter for individual client sessions that are part of a larger global session. The global session is created after the creation of the first protocol session and exists across the creation of future sessions on other protocols and other converged applications. Logical names and global session tokens are utilized to manage the various global sessions handled by the edge server.

Abstract: A mechanism for managing associations in the CIM model are proposed. An association is modeled by a particular class, which includes two or more references to other classes; the association is implemented by a corresponding provider. Whenever a management application (such as a performance monitor) needs to access the association, a corresponding request is transmitted to the provider. In response thereto, the provider enumerates all the resource objects instantiating the references of the association, and creates an instance of the association for any combination. The provider further sets a property of each instance of the association, according to dynamic characteristics of the corresponding resource objects. In this way, an active association is provided, allowing cross-analysis of the resource objects participating in the association.

Abstract: A mechanism for switching between multiple copies of a software program on a computer system is provided. The mechanism includes detecting a plurality of copies of the software program on a computer system, receiving input selecting one of the detected plurality of copies of the software program to be a default copy, and determining whether the selected copy of the software program is a current default copy on the computer system. If the selected copy of the software program is not the current default copy on the computer system then, the mechanism further includes demoting the current default copy to be an alternate copy, and promoting the selected copy of the software program to be a next current default copy.

Abstract: Mechanisms for enforcing change control in operations performed by operational management products (OMPs) are provided. The mechanisms automate the checking of a request-for-change (RFC) state by an OMP when the OMP is installed in an environment where a change management database (CMDB) has been installed and certain resources or operations have been placed under strict change control. The OMPs of the illustrative embodiments require an RFC identifier to be specified when a change operation of the OMP is invoked. The RFC identifier is used by the OMP to access a service management system so that the OMP may determine if the RFC identifier is valid, IT resources are in the correct state, and the change is scheduled to be performed at the current time. If these checks are passed, then the change operation associated with the RFC is permitted to occur.

Abstract: The present invention provides mechanisms that enable application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor. In one aspect of the present invention, a mechanism is provided for handling user space creation and deletion operations for creating and deleting allocations of linear block addresses of a physical storage device to application instances. For creation, it is determined if there are sufficient available resources for creation of the allocation. For deletion, it is determined if there are any I/O transactions active on the allocation before performing the deletion. Allocation may be performed only if there are sufficient available resources and deletion may be performed only if there are no active I/O transactions on the allocation being deleted.

Abstract: Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.

Abstract: A persistent authenticating mechanism to map real world object presence into virtual world object awareness are provided. The illustrative embodiments provide a mechanism by which the presence of a real world object is detected and, while the real world object's presence continues to be detected, it is made available for use in a virtual environment. The detection of the real world object provides an identifier of the object which is correlated with information regarding how to represent the object in the virtual environment, how the object may be utilized in relation to other objects in the virtual environment such that the real world object is modeled in the virtual environment, and the like. The detection of multiple real world objects may be performed and identification of each of the multiple objects may be used to determine how these objects may be utilized together in the virtual environment.

Abstract: Mechanisms for hot-plug/remove of a new component in a running communication fabric, such as a PCIe fabric, are provided. With these mechanisms, the addition of a new component in the fabric is detected and an event is sent to a multiple root fabric configuration manager. The multiple root fabric configuration manager gathers information about the new component and updates its I/O component tree structure in its configuration data structure to include the new component. The new component may then be utilized via the updated configuration data structure. When a component is to be removed, the multiple root fabric configuration manager receives an event indicating the component to be removed, determines which branches of the tree structure are affected by the removal, and updates its configuration data structure accordingly to remove the component and its associated components from the virtual plane of the removed component.

Abstract: Mechanisms for providing visual keyboard guides according to a programmable set of keys are provided. With the mechanisms of the illustrative embodiments, a user may select for which keys of a keyboard the user wishes to receive visual guides on a display of a data processing device associated with the keyboard. Thereafter, when the user's fingers are in proximity to keys of the keyboard, a comparison of the keys in proximity to the user's instrument to the keys for which visual guides are to be provided is made. If the keys in proximity to the user's instrument match keys for which visual guides are to be provided, a visual guide is displayed on the display of the data processing device. A graphical user interface may be provided to the user for setting which keys are to have associated visual guides.

Abstract: A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

Abstract: A computer implemented method is provided for a bi-directional data mapping tool. The method for mapping between at least two data models comprises selecting a source including a first data model, selecting a target including a second data model and defining a relationship between the data in the source and the data in the target. The method further comprises generating a bi-directional map from at least portions of the source, the target, and the defined relationship.

Abstract: Mechanisms for providing a social network aware input dictionary are provided. A social network of users is monitored to determine the words and terms utilized by the users as part of their communication and interaction within the social network. Words and terms are ranked, or prioritized, within the social network based on a determined increase/decrease in popularity of the words/terms as determined from the monitoring of the social network. Based on the ranking of these words/terms, individual input dictionaries associated with devices used by the users of the social network may be automatically updated to include/remove these words/terms and/or increase/decrease a relative priority of the words/terms within the input dictionaries. Such automatic updating may be performed regardless of whether the particular user has used the word/term or not.

Abstract: Mechanisms for migration of a virtual endpoint from one virtual plane to another are provided. With these mechanisms, when a management application requests migration of a virtual endpoint (VE) from one virtual plane (VP) to another, a fabric manager provides an input/output virtualization intermediary (IOVI) with an interrupt to perform a stateless migration. The IOVI quiesces outstanding requests to the virtual functions (VFs) of the VE, causes a function level reset of the VFs, deconfigures addresses in intermediary switches corresponding to the VP, and informs the fabric manager that a destination migration is requested. The fabric manager sends an interrupt to the destination IOVI which performs a function level reset of the destination VFs and reprograms the intermediary switches with the addresses of the destination VP. The destination VFs may then be placed in an active state.

Abstract: A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address.

Abstract: A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.

Abstract: Method and system for dynamically checking an access control list during the data transfers between a client web browser and a web server. The method and system allow checking of access control list by an application firewall, independent from the web application. The rules, upon which the checking is based, can be easily updated without affecting the web application.