Abstract: Mechanisms for evaluating at least one setting for a database system are disclosed. The mechanisms include providing at least one configuration derivative including the at least one setting. The configuration derivative is uncommitted. The mechanisms also include running the database system for a period of time. The database system is run using a committed configuration including a plurality of settings for the database system. The mechanisms also include collecting data on performance of the database system based on the at least one configuration derivative during the running of the database.

Abstract: An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.

Abstract: Mechanisms for controlling asynchronous clock domains to perform synchronous operations are provided. With these mechanisms, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.

Abstract: Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

Abstract: Mechanisms for reducing memory overhead of a page table in a dynamic logical partitioning (LPAR) environment are provided. Each LPAR, upon its creation, is allowed to declare any maximum main memory size for the LPAR as long as the aggregate maximum main memory size for all LPARs does not exceed the total amount of available main memory. A single page table is used for all of the LPARs. Thus, the only page table in the computing system is shared by all LPARs and every memory access operation from any LPAR must go through the same page table for address translation. As a result, since only one page table is utilized, and the aggregate size of the main memory apportioned to each of the LPARs is limited to the size of the main memory, the size of the page table cannot exceed the size of the main memory.

Abstract: A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A system and associated method for building a network model of a network for a network management application. The network management application discovering a router discovers peering routers using network reachability information in a routing protocol. Undiscoverable peering routers are created within the network model by the network management application from network reachability information. Also a local subnet for the router, a remote subnet for a peer, a remote interface between the router and the peer also may be created to model the network in a network management application from information from the routing protocol.

Abstract: A mechanism for structured query language tagging is provided. The mechanism comprises a parsing unit for parsing a structured query language string into components, an analysis unit for analyzing the components and applying associated tags to the components, and a string generation unit for concatenating the components with associated tags into a new string.

Abstract: Mechanisms for external and distributed protection of Web application data against prying, tampering, and impersonation using cryptographic mechanisms are provided. The protection is offered opaquely so as to not expose the cryptographic mechanism to the Web application. Protection against prying prevents users from looking at data the Web application considers private. When protected against prying, protect data may be sent to the client but the user will not be able to understand it. Protection against tampering, guaranties the Web application that the data it is receiving originated from a trusted source, usually the Web application itself. A user session state stored client-side is a good candidate for tampering protection. Protection against impersonation ensures the Web application that the data it is receiving comes from a specific user.

Abstract: Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.

Abstract: Mechanisms for distributing rate limits and tracking rate consumption across members of a cluster are provided. One member of the cluster is responsible for controlling the distribution of rate capacity across members of the cluster. Rate capacity may be distributed in a hierarchical fashion to account for the needs of the various services, applications, and/or operations provided by the cluster members. A hierarchical tree structure may be formed by distributing rate capacity among a plurality of nodes arranged at a global, service, application or operation level of the tree. In some cases, rate capacity may also be distributed at a requester level to account for the needs of requesters who are granted access to the services, applications and operations provided by the cluster members.

Abstract: A network is provided herein comprising a plurality of network resources, and at least one network cluster having a plurality of cluster members. Each member of the cluster may be configured for utilizing one or more of the network resources and for tracking usage thereof. For example, each member of the cluster may include one or more token buckets for tracking that member's usage of the network resources. At least one member of the cluster (i.e., a “reservation coordinator”) may include a first set of computer-executable instructions for receiving network traffic destined for a particular network resource at a first rate (i.e., a maximum average sustained rate). In addition, the reservation coordinator may include a second set of computer-executable instructions for distributing the first rate among at least a subset of the cluster members.

Abstract: Mechanisms for thresholding system power loss notifications in a data processing system are provided. Power loss detection modules are provided in a data processing system having one or more data processing devices, such as blades in an IBM BladeCenter® chassis. The power loss detection modules detect the type of infrastructure of the data processing system, a position of a corresponding data processing device within the data processing system, and a capability of the data processing system to provide power during a power loss scenario. The detection module detects various inputs identifying these types of data processing system and power system characteristics and provides logic for defining a set of behaviors during a power loss scenario, e.g., behaviors for sending system notifications of imminent power loss. The detection of the various inputs and the defining of a set of behaviors may be performed statically and/or dynamically.

Abstract: A hypervisor, during device discovery, has code which can examine the south-side management data structure in an adapter's configuration space and determine the type of device which is being configured. The hypervisor may copy the south-side management data structure to a hardware management console (HMC) and the HMC can populate the data structure with south-side data and then pass the structure to the hypervisor to replace the data structure on the adapter. In another embodiment the hypervisor may copy the data structure to the HMC and the HMC can instruct the hypervisor to fill-in the data structure, a virtual function at a time, with south-side management data associations. The administrator can assign south-side data, such as a MAC address for a virtual instance of an Ethernet device, to LPARs sharing the adapter. Thus, a standard way to manage the south-side data of virtual functions is provided.

Abstract: Mechanisms for burst traffic smoothing for Session Initiation Protocol (SIP) processing elements are provided. A dispatch queue management engine determines whether a received packet is a TCP or UDP packet. If the packet is a TCP packet, the packet is automatically added to the dispatch queue. If the packet is a UDP packet, a value for a drop function ƒ is generated and a random or pseudo-random number r is generated. If r has a predetermined relationship to ƒ, then the UDP packet is added to the dispatch queue, otherwise the UDP packet is discarded. The value for ƒ is based on the current dispatch queue load, the network quality, the retransmission rate, and the allowable drop rate. Thus, the determination as to whether to drop UDP packets or not is configurable by an administrator and also adaptable to the current network and dispatch queue conditions.

Abstract: Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

Abstract: Mechanisms for performing an inventory scan of target data processing systems for ascertaining the presence therein of prerequisite resources are provided. The prerequisite resources are resources necessary for the execution, by the target data processing systems, of predetermined activities. The mechanisms may send to a target data processing systems a request for performing a selected activity of the predetermined activities and associate with the request at least one signature of at least one prerequisite resource different from the prerequisite resources required for performing the selected activity. The signature may include information allowing the target data processing system to locate where the prerequisite resource is to be searched for. Upon receiving, from the target data processing systems a result of the search of the prerequisite resource, the mechanisms may further update information to indicate the presence of the prerequisite resource in the target data processing system.

Abstract: A method, computer program product, and system for managing statistical views in a database system are provided. The method, computer program product, and system provide for collecting data relating to optimization and execution of a workload in the database system and automatically generating a set of one or more statistical views based on the collected optimization and execution data.

Abstract: A data warehouse solution system comprises a metadata model, a user interface and an engine. The metadata model has an information needs model including metadata regarding information needs for building reports by users, and a data information model including metadata describing data that is available for building reports. The user interface has a customer user interface for presenting the information needs model to the users for report generation, and a modeling user interface for presenting the data information model to the users for manipulating data warehouse objects. The engine has a report management service unit for providing report management service using the information needs model, and a data management service unit for providing data management service including generation of a data warehouse using the data information model.

Abstract: Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission.