Abstract: A system for preparing a first multimedia stream, for use with an environment comprising a repository for storing a plurality of tracks. Each track may be associated with at least one second multimedia stream. A track may comprise a single type of data (e.g., audio, video, etc.). The method may comprise receiving a request comprising an associated parameter (e.g., a position parameter) and determining at least two of the plurality of tracks associated with the parameter. The at least two tracks may have associated information that matches the position parameter. Responsive to determining the at least two tracks, the determined at least two tracks may be collated in order to generate the first multimedia stream.

Abstract: A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

Abstract: Mechanisms for preventing IP spoofing and facilitating parsing of private data areas in system and network connection requests are provided. With these mechanisms, an identifier, such as the high order bit of a Q_Key, is utilized to determine if a communication connection request originates with a privileged process. A second identifier is used to specify whether a private data area of a communication connection request utilizes predefined fields of a predefined structure or format. Only when the first identifier specifies that the request originates from a privileged process is the processing of the request permitted to be performed. Based on the setting of the second identifier, specific information is retrieved from the predefined fields of the private data area for use in establishing the requested communication connection.

Abstract: In remote control systems (as in many other circumstances) the color representation of a bitmap is one of the heaviest factor in term of storage occupation and speed of transmission. Often, only a limited number of colors is actually used by a bitmap, so that the bit pattern of the single pixels is bigger than what is really needed to represent all the possible different colors. With the present invention, in case the number of colors does not exceed a predetermined thresholds, a palette table containing all the colors used in the bitmap is created. The pixel representations in the bitmap are then replaced by a pointer to the corresponding entry in the palette table. This allows to reduce the total size of the bitmap. The reduced bitmap is then transmitted together with the associated palette table. The receiving computer (the controller in a remote control system) is able to rebuild the original bitmap with the help of the palette table.

Abstract: Mechanisms for differentiating traffic types in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding virtual link in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure.

Abstract: Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: A context menu including a group copy function is displayed and, when the function is selected, all parent nodes of a node corresponding to the input field the pointing device is positioned over are displayed as alternatives to be copied. In response to selection of a parent node for copying by the pointing device, data in all nodes lower than the parent node are copied into a memory. In response to clicking by the pointing device in the input field selected as a pasting destination, a data type of the input field selected as the copying destination and the data type of the data copied into the memory are compared, and if the same, all of the data copied into the memory are pasted in the fields lower than the input field previously selected as the pasting destination.

Abstract: A laminate assembly comprises a base layer, a substantially transparent inclusion layer disposed above the base layer and having a plurality of included objects disposed within the inclusion layer, and a substantially transparent top layer disposed above the inclusion layer. The base layer, inclusion layer, and top layer are formed in succession.

Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract: A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.

Abstract: Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.

Abstract: Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

Abstract: A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

Abstract: Mechanisms for collective send operations on a system area network are provided. The mechanisms of the illustrative embodiments provide for the creation, modification, and removal of collective send queues (CSQs) that allow the upper level protocol (ULP) used by a consumer to send the same message to a collective set of queue pairs (QPs). In order to use the transport services of a CSQ, a consumer process posts a write work request (WR) to the CSQ. The write WR causes a write work queue element (WQE) to be generated and placed in the CSQ. A channel interface (CI) is provided that effectively copies the write WQE to all of the send queues (SQs) of the QPs in the QP set associated with the CSQ. When all the QPs complete processing of their respective write WQEs, the HCA releases all data segments referenced by the write WR.

Abstract: A solution is proposed for testing a software application. The test includes the execution of a series of test cases, each one involving the application of a predefined test input to the software application. The software application generates a corresponding output in response to this test input. A result of the test case is determined by comparing the actual output provided by the software application with an expected output thereof. The expected output of the test case is determined automatically. For this purpose, multiple auxiliary sources are exploited, such as other software applications different from the one under test. Each auxiliary source receives a corresponding input, derived from the test input, which is intended to cause the auxiliary source to provide the same expected output as the software application. The expected output is then estimated according to the actual outputs provided by the different auxiliary sources.

Abstract: A hybrid superconductor-optical quantum repeater is provided. The hybrid superconductor-optical quantum repeater comprises an optical subsystem configured to receive an optical signal via an optical channel and a superconductor subsystem coupled to the optical subsystem. The optical subsystem and superconductor subsystem are coupled to one another via a microwave transmission medium. The optical subsystem is configured to receive an optical signal via the optical channel and down-convert a photon of the optical signal to a microwave photon in a microwave output signal that is output to the superconductor subsystem via the microwave transmission medium. The superconductor subsystem stores a quantum state of the microwave photon and transmits the microwave photon along an output channel from the superconductor subsystem.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

Abstract: A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.

Abstract: A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.