Patents Represented by Attorney Steven A. Shaw

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  • Apparatus and method for transparent USB-to-1394 bridging and video delivery between a host computer system and a remote peripheral device
    Patent number: 6356968
    Abstract: The present invention provides an apparatus and method for transmitting serial data bits in a computer system having both an IEEE 1394 bus and a universal serial bus. The arrangement comprises a networked entertainment system comprising a host computer system and a remote peripheral consumer electronics device. The host system includes a processor, a bus, a memory, and a graphics card. A host interface circuit is coupled to the host system to provide an interface with a remote peripheral device. A remote interface circuit is coupled to the remote peripheral device to provide an interface with the host system. The host interface circuit and the remote interface circuit are connected to each other by an IEEE 1394 bus cable. The host interface circuit provides a USB port for connecting a USB device to the host system. The remote interface circuit provides USB ports for connecting USB devices.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: March 12, 2002
    Assignee: Cirrus Logic, INC
    Inventor: Jakob Kishon
  • Memory with pipelined accessed and priority precharge
    Patent number: 6282603
    Abstract: A memory 200 comprises a first memory bank 201a including an array of memory cells 202a and row and column address circuitry 203a, 205a for addressing a location within the array 202a. The memory further includes a second memory bank 201b including an array of memory cells 202b and row and column address circuitry 203b, 205b for addressing locations within the array 202b. Row and address column circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks. Furthermore, circuitry places the memory into priority precharge in response to a priority signal, where the priority precharge terminates a current access to the memory and some addresses required for a priority access are selectively pipelined during priority precharge.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: August 28, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: G. R. Mohan Rao
  • Rate control techniques for efficient high speed data services
    Patent number: 6219343
    Abstract: Methods for controlling data rate allocations to data packet users transmitting packet data over a CDMA cellular communication network are defined which comprises the steps of: evaluating traffic channels and radio capacity allocated for packet data services within the network to determine an available resource for a packet data transmission; employing a rate control algorithm to determine a data rate allocation for the packet data transmission; and limiting the transmit power of a transmitter to provide the determined data rate allocation for the packet data transmission. The methods include a rate control algorithm which determines data rate allocation using a transmission power budget technique and a rate control algorithm which determines data rate allocation using a current system load technique.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: April 17, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Zhichun Honkasalo, Janne Parantainen, Lin Ma
  • Portable communications and data terminal operating to optimize receipt of both incoming CDPD and AMPS messages
    Patent number: 6157836
    Abstract: A portable radio telephone handset operates as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the handset. The handset distinguishes between paging signals indicating CDPD mode communications and those indicating analog cellular communications. The handset also automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. The handset maintains an active status on a CDPD communication channel during a "sleep mode", when the handset can carry out AMPS activity.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: December 5, 2000
    Assignee: Pacific Communication Sciences, Inc.
    Inventor: Russell P. Cashman
  • Priority storage system for fast memory devices
    Patent number: 6121974
    Abstract: A process and implementing computer system for graphics applications in which information files such as texture maps (TMs) are prioritized and stored in a relatively fast local memory. The method of prioritization includes initially sorting the information files by order of the frequency with which corresponding graphics primitive elements are called by the application. The priority is adjusted such that the smaller TMs get an increase in their priority so that more TMs may be placed in faster graphics memory. Thereafter among similarly prioritized groups of information files, the larger of the files are first stored in the fast local memory and the remaining files are marked for storage in the system memory after the fast local memory has been fully utilized.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: September 19, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher William Shaw
  • Fine alignment IC handler and method for assembling the same
    Patent number: 6111420
    Abstract: The apparatus of the present invention includes a frame for attaching the clamp of a hand test socket to a workpress assembly of a high-speed IC handler. The frame attaches to a workpress assembly. Utilizing the clamp of a test socket recycles frequently unused test socket parts and eliminates the need for custom fabricated workpress assembly components. The method for adapting the hand test socket for use on the workpress assembly includes the steps: providing a test socket having a base and a top cover, the top cover including a clamp; removing the top cover and the clamp; configuring the clamp for use in a workpress assembly; and attaching the clamp to the workpress assembly.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: August 29, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Mark P. Kelley, Yakov A. Bobrov
  • Circuits, systems and methods for interfacing processing circuitry with a memory
    Patent number: 6108015
    Abstract: A processing system 100 is provided which includes processing circuitry 103 fabricated on an integrated circuit chip 107. An internal memory 104a is also fabricated on chip 107. A first first-in/first-out memory 201 is provided having an input for receiving data retrieved from the internal memory 104a and an output for providing data to processing circuitry 103. An external memory 104b is provided. A second first-in/first-out memory 202 includes an input for receiving data retrieved from the external memory 104a and an output for providing data to the processing circuitry 103.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: August 22, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Randolph A. Cross
  • PCI bus master retry fixup
    Patent number: 6104876
    Abstract: A technique for providing PCI bus mastering compatibility for legacy PCI bus devices which may not support PCI bus mastering RETRY protocols. DLDMM provider software in a device driver for a target device may provide a callback signal at a callback address to DLDMM client software in a device driver for a bus mastering PCI device. The callback address may be used by the DLDMM client software to signal the bus mastering PCI device to suspend operation in the event of an interrupting event. The bus mastering PCI device may then generate in driver software a RETRY signal to the device driver of the target device. If the interrupting event is over, a signal may be sent by the DLDMM provider software in response to the RETRY signal to the DLDMM client software indicating that the bus mastering device may resume operation. The bus mastering device may then resume operation where left off.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 15, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Daniel Daum, Jeffrey G. Ort
  • Host DMA through subsystem XY processing
    Patent number: 6088046
    Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: July 11, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Michael Kerry Larson, Timothy James McDonald
  • Programmable core-voltage solution for a video controller
    Patent number: 6078319
    Abstract: An integrated circuit such as a video controller may be provided with core logic circuitry using CMOS technology which may be operated at different supply voltages such as 3.3 or 5 Volts. At lower supply voltages, the CMOS circuitry may run slower. For a video controller, certain higher resolution, pixel depths, and refresh rates may require high speed operation of the video controller. A monitoring circuit monitors the video mode, pixel resolution, pixel depth, and refresh rate and determines which supply voltage may be used to operate the video controller at such levels. An output signal from the monitoring circuit may be used by a switching circuit to supply an appropriate supply voltage to the integrated circuit. At lower performance levels, the integrated circuit may be operated at lower voltages to conserve power.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: June 20, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Vlad Bril, Sagar Waman Kenkare, Thomas Shieh-Luen Ho, Edmund Christian Strauss
  • Tracking of graphics polygon data from different clock domains in a graphics processor
    Patent number: 6061073
    Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates from a first clock domain a display list which includes poly parameter data for rendering the graphics primitives. A graphics processor which includes internal fetch and store unit stores and processes the polygon parameter data in a second clock domain different from the first clock domain. To ensure the complete processing of polygon data from the first clock domain in the second clock domain, the graphics processor includes a polygon data tracking logic for tracking the flow of the polygon data in the graphics processor. The polygon data tracking logic includes an up/down counter which up counts polygon data fetched in the graphics processor and down counts the polygon data when the polygon data is processed in the graphics processor.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: May 9, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Michael K. Larson
  • Circuits, systems and method for address mapping
    Patent number: 6058464
    Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: May 2, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: Ronald T. Taylor
  • Memory architecture using content addressable memory, and systems and methods using the same
    Patent number: 6041389
    Abstract: A memory 200 including an array 202 of addressable memory cells and a content addressable memory cell 207/300 for comparing a received select bit with a stored select bit and enabling access to addressed ones of the memory cells in response.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: March 21, 2000
    Assignee: E Cirrus Logic, Inc.
    Inventor: G. R. Mohan Rao
  • Cordless headset
    Patent number: D445415
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: July 24, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Mikael Jaakkola
  • Key array for a communicator
    Patent number: D448367
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: September 25, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Panu M. P. Johansson
  • Function key for a communicator
    Patent number: D448386
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: September 25, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Panu M. P. Johansson
  • Handset
    Patent number: D448742
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 2, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Jeffrey Higashi, Kelley Ann Chao-Fei Ching Lee, Dimitre Mehandjiysky
  • Keypad for a handset
    Patent number: D451912
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: December 11, 2001
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Jeffrey Higashi, Kelley Ann Chao-Fei Ching Lee, Dimitre Mehandjiysky
  • Keypad for a handset
    Patent number: D454342
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: March 12, 2002
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Kelley Ann Chao-Fei Ching Lee
  • Handset
    Patent number: D455413
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 9, 2002
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Kelley Ann Chao-Fei Ching Lee