Abstract: A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.

Abstract: A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. Techniques for operating programming, erasing, and characterizing the memory cell with multiple oxide thicknesses are discussed.

Abstract: A system enabling an application programmer to construct a plurality of application programs for communicating with a plurality of remote machines of a plurality of machine types, each of the plurality of remote machines having remotely accessible data and remotely performable operations includes a computer system with a memory, a processor, and a mass storage device, the computer system for storing programs, class declarations, and class libraries in an object-oriented programming language, means for compiling files containing source-code representations of application programs in the object-oriented programming language, implementations of a hierarchy of data description classes, each implementation for describing a set of data and for describing methods for manipulating the set of data, implementations of a hierarchy of remote data description classes, each implementation for describing data items contained in one of the plurality of remote machines and for describing methods for accessing the data items,

Abstract: A distributed group activity network system and corresponding method over a computer network. It synchronizes and provides access by system users to shared data files of a group activity. The distributed group activity network system comprises one or more server computers and client computers that are connected to the server computer(s) by network connections. Each of the server computers comprises a network server and a memory system. The network server runs on the server computer and provides basic network services that are available at the server computer. The memory systems of the server computers store synchronization files and shared data files of the group activity. Each of the client computers comprises a memory system and a system module running on the client computer.

Abstract: A hardware design language V++ is described. V++ provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V++ each program is directly interpreted as a network of communicating finite state machines. The composition of two V++ programs is a V++ program, with well-defined, deterministic semantics.

Abstract: Document query and search techniques in which documents to be searched are “decomposed” into “zones,” with each zone representing a grouping of text or graphical image or a combination thereof. The zones are defined within, and associated with a document page. One or more zones in the documents are selected for annotation with text (e.g., keywords), image features, or a combination of both. Document query and search are based on a combination of text annotations and image features. In one implementation for operating a document retrieval system, an unindexed (also referred to as a “query” or “search key”) document is captured into electronic form and decomposed into a number of zones. The zones can be segmented into text zones and image zones. Descriptors are formed for at least one of the zones. The descriptors can include text annotations for text zones, and text annotations and image features for image zones.

Abstract: An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.