Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Abstract: A charge pump circuit includes at least one switching transistor and a level-shifter. The level-shifter has a cross-coupled pair of transistors. The level-shifter shifts a voltage of a first input signal to generate a level-shifted signal. The level-shifted signal controls a conductive state of the switching transistor to regulate an output voltage of the charge pump. A feedback loop circuit includes a detector and a charge pump. The detector compares an input signal to a feedback signal to generate first and second output signals. The charge pump includes at least two thin-oxide switching transistors and a level-shifter in another embodiment. The level-shifter shifts a voltage of the first output signal of the detector to generate a level-shifted signal. The two switching transistors are driven by the level-shifted signal and the second output signal of the detector to regulate an output voltage of the charge pump.

Abstract: A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

Abstract: A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.

Abstract: A verifiable security mode is provided for securing data on a storage device, such as a hard disk drive. When the verifiable security mode is enabled, only authenticated accesses to data stored on the storage device are permitted after entering a password. An end user is prevented from disabling the verifiable security mode. The verifiable security mode can be set to allow or disallow an administrator from disabling the verifiable security mode. The verifiable security mode can be implemented, for example, in firmware on a hard disk drive (HDD).

Abstract: A data storage apparatus includes a data storage medium, a write element, a non-volatile cache memory circuit, and a controller circuit. The controller circuit is configured to record data on the data storage medium in groups of overlapping tracks using the write element. The controller circuit is configured to store a shingle block of data from a subset of the overlapping tracks in the non-volatile cache memory circuit, while at least a portion of the data in the shingle block of data is updated.

Abstract: Voltage regulating systems are provided that adjust their output control signals in response to feed-forward information that is indicative of deterministic changes in the load current. A feed-forward circuit provides a feed-forward signal in response to an input signal generated from a source that is external to the voltage regulating system. The voltage regulator systems can proactively respond to the predictive information by adjusting their output, thereby improving the regulation tolerance to dynamic loading. As an example, the feed-forward information can include signals indicating multiple deterministic events that affect the load. Signals from multiple events can be summed together to generate a feed-forward term. As another example, the voltage regulating systems can be responsive to feedback information and feed-forward information from internal to the regulator, in addition to external deterministic information.

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Abstract: A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.

Abstract: A phase interpolator circuit includes first and second low pass filter circuits and a multiplier circuit. The first low pass filter circuit increases a common mode voltage of a clock signal to generate a first varying signal. The second low pass filter circuit increases a common mode voltage of a clock signal to generate a second varying signal. The first low pass filter circuit can include a first variable capacitance, and the second low pass filter circuit can include a second variable capacitance. The multiplier circuit has a first input coupled to the first low pass filter circuit and a second input coupled to the second low pass filter circuit. The multiplier circuit generates a third varying signal in response to the first and the second varying signals. The phase interpolator circuit generates a phase shift in the third varying signal.

Abstract: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

Abstract: Some embodiments include a storage device with a storage medium having a memory capacity. The storage device also includes virtual storage device firmware that is configured to directly respond to commands from a guest operating system in a virtual machine for accesses to a subset of the memory capacity of the storage medium when a virtual storage device is enabled.

Abstract: An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.

Abstract: A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.

Abstract: Techniques are provided for identifying the servo sectors in a track on a data storage device. A data storage device identifies the servo sectors in a track by reading distributed index bits from multiple servo sectors in a track. The data storage device analyzes only one index bit from each servo sector to identify the index of a track. In some embodiments, the index of a track can be identified after examining the index bits stored in a particular number of consecutive servo sectors, even in the presence of errors. The index bits in each track can have an error tolerance with a minimum Hamming distance greater than one. In other embodiments, a data storage device compares a sliding window of the index bits read from the servo sectors to all possible N-bit vectors that exist within a pattern of the index bits stored on a track.

Abstract: A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.

Abstract: The conventional cascode circuit can be improved by adding another transistor in series. The added transistor may use the body effect to reduce supply voltage variations across the cascode transistor as the supply voltage varies. The added transistor reduces impact ionization in the cascode transistor.

Abstract: Enhancements to the functionality of a file system are provided. A file system can provide an additional level of error correction, in addition to the error correction provided by a data storage device. An extension to the metadata area in a file system can store index information about data files that the file system can use to reduce the time it takes to access the files. A file system can use extended metadata to store conditional access information for data files stored in the file system. A data storage device can also examine and characterize the data being stored in order to categorize a user's files automatically. Modules can be loaded into a file system to provide new functionality to the file system. The modules can load additional modules to extend their functionality.