Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.

Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Abstract: Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

Abstract: A clock signal generator circuit that receives periodic signals has a delay circuit, first and second multiplexers, and flip-flops. The delay circuit delays the periodic signals to generate delayed signals. The first multiplexer selects one of the delayed signals in response to a first select signal to generate an output clock signal. The second multiplexer selects one of the periodic signals in response to a second select signal. The flip-flops generate the first and the second select signals in response to the periodic signal selected by the second multiplexer.

Abstract: An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a calibration number of the fine capacitors having a combined capacitance that most closely matches a capacitance of one of the coarse capacitors.

Abstract: A non-volatile memory circuit includes a first inverter, a second inverter coupled to the first inverter, a first programmable non-volatile resistor coupled to the first inverter, and a first access device coupled to the first programmable non-volatile resistor. According to some embodiments, a second programmable non-volatile resistor is coupled to the second inverter, and a second access device is coupled to the second programmable non-volatile resistor. The access devices can be, for example, transistors or diodes.

Abstract: A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Abstract: Digitally controlled delay-locked loops can have a phase detector, control logic, and a delay chain. The control logic generates digital signals in response to an output signal of the phase detector. The delay chain generates a delay that varies in response to the digital signals. In some embodiments, the control logic maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop. In other embodiments, the delay of the delay chain varies by a discrete time period in response to a change in logic states of the digital signals, and the maximum phase error between a phase of the reference clock signal and a phase of the feedback clock signal is less than the discrete time period when the digitally controlled delay-locked loop is in a lock mode.

Abstract: A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.

Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.

Abstract: A data storage device has a data storage medium configured to store a first version of data in parent sectors. The data storage device is configured to store a second version of the data in child sectors. The child sectors have the same logical block addresses as the parent sectors. A host operating system can read data from or write data to the child sectors by sending logical block addresses and a sector set number to the data storage device. The logical block addresses and the sector set number identify the child sectors. In response to receiving a request to access the child sectors, the data storage firmware identifies physical addresses that correspond to the logical block addresses and the sector set number. The data storage device uses the physical addresses to identify the location of the child sectors.

Abstract: Phase detection circuitry in a delay-locked loop compares a periodic input signal to a feedback signal. The phase detection circuitry generates a delay signal that controls delays of the delay circuits. Two or more output signals of the delay circuits are transmitted to an input of the phase detection circuitry. The delay-locked loop can be configured so that the period of the periodic input signal divided by a delay of one of the delay circuits equals a non-integer rational number when the phase and frequency of the periodic input signal are constant. A frequency multiplier can be coupled to the delay circuits to generate a periodic output signal. The periodic output signal has an average frequency that is a product of the frequency of the periodic input signal multiplied by a fractional non-integer number when the phase and frequency of the periodic input signal are constant.

Abstract: An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

Abstract: Greater error protection is provided to error-prone bits that are generated from irregular soft-decoded error correction codes. Error protection is increased to error-prone bits that of interest in a particular system (e.g., parity check bits). One or more extra bits are added to each codeword in the encoding process. The one or more extra bits correspond to lower weights. The one or more extra bits are discarded after each codeword is decoded.

Abstract: A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.

Abstract: A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circuit generates dynamic control signals in response to the delay compensation signals. The programmable delay circuit is configurable to delay a signal transmitted through an external terminal of the circuit by a delay that is selected by the dynamic control signals.

Abstract: A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.