Abstract: A system for enhancing the reliability of file systems is provided. In particular embodiments, the system includes a data storage device that includes one or more journal blocks, one or more primary metadata blocks, and one or more mirror metadata blocks. The system also includes a file system that writes metadata to the one or more journal blocks before writing the metadata to both the one or more primary metadata blocks and to the one or more mirror metadata blocks.

Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Abstract: Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

Abstract: Circuits and methods are provided for write through drivers in disk drive systems. A write through driver is a transceiver that includes a write driver circuit and a receiver circuit. The write driver drives a current signal to a write element through a first conductive interconnect. The write element writes data patterns to a magnetic hard disk in response to the current signal from the write driver circuit. The current signal returns to the receiver circuit through a second conductive interconnect. The return signal can be used for the diagnosis of write-safe conditions.

Abstract: A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

Abstract: A circuit comprises a programmable voltage regulator and an oscillator. The programmable regulator generates a regulated supply voltage using an input voltage and changes the regulated supply voltage from a first voltage to a second voltage in response to a first control signal. The first and the second voltages are generated using charge from the input voltage. The regulated supply voltage drives the oscillator. The oscillator varies a frequency of a periodic output signal within a frequency range in response to changes in a control voltage. The frequency range of the periodic output signal varies when the first control signal causes the regulated supply voltage to change from the first voltage to the second voltage.

Abstract: A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.

Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.

Abstract: A charge pump circuit includes switch circuit modules and current modules. The number of switch circuit modules that are coupled to receive current from one of the current modules is variable. The output current of the charge pump circuit increases as more of the switch circuit modules are coupled to receive current from the current modules. The net on-resistance of the switch circuit modules decreases as more of the switch circuit modules are coupled to receive current from the current modules. Charge coupling caused by the net parasitic gate-to-drain capacitance of switching transistors in the switch circuit modules is reduced at smaller output current settings of the charge pump circuit.

Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.

Abstract: Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

Abstract: Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, a plurality of modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: Techniques are provided for calibrating parallel on-chip termination (OCT) impedance circuits. An on-chip termination (OCT) calibration circuit generates first calibration codes and second calibration codes. The first calibration codes control the conductive states of first transistors that are coupled in parallel between a supply voltage and a first terminal. The second calibration codes control the conductive states of second transistors that are coupled in parallel between the first terminal and ground. The OCT calibration circuit selects a first calibration code and a second calibration code and transmits the selected calibration codes to third and fourth transistors to control a parallel on-chip termination impedance at a pin.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

Abstract: Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

Abstract: Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.

Abstract: Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk or impedance. Vias that conduct input or output signals can be placed next to vias that provide return paths for the input or output signals to reduce cross-talk. The vias that provide the return paths can conduct, for example, ground signals, power supply signals, or both. Vias that conduct power supply signals can be placed next to vias that provide return paths for the power supply signals to reduce impedance. The vias that provide the return paths for the power supply signals can conduct, for example, ground signals. The via configurations reduce cost and increase yield, and the via configurations are modular.

Abstract: Techniques are provided for capturing external signals at output pins on a programmable logic integrated circuit (IC) during a boundary scan test. A JTAG sample signal is routed to an input/output block on a chip and active during a JTAG sampling phase. An input buffer coupled to an output pin is turned on during the JTAG sample phase. Logic gates enable the input buffer in response to the JTAG sample signal so that the input buffer can capture a signal on the pin. The input buffer is turned off after the JTAG sampling phase to conserve power. The output buffer coupled to the pin that receives the test signal is tristated to prevent contention during the JTAG sampling phase. The techniques of the present invention can be used to test board level interconnects in less time and are easy to implement.