Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.

Abstract: A calibration circuit block includes a first resistor network, a second resistor network, and a feedback loop. The first resistor network includes a set of transistors and receives a constant current from a constant current source. The second resistor network receives a tracking current from a tracking current source. The impedance of the second resistor network changes with temperature and process variations on the integrated circuit. The tracking current source compensates for variations in the impedance of the second resistor network that are caused by process and temperature variations to maintain a constant reference voltage at the second resistor network. The feedback loop generates calibration control signals for controlling the conductive states of the transistors in the first resistor network. The feedback loop adjusts the calibration control signals to maintain a constant impedance in the first resistor network.

Abstract: Techniques are provided for implementing freeze logic on programmable logic blocks. The output signal of a register in each programmable logic block is driven to a predefined state in response to a freeze signal. The freeze signal also causes a multiplexer in each programmable logic block to select the output signal of the register. The multiplexer drives an output signal of the programmable logic block to a predefined state to eliminate contention between circuit elements. The freeze logic requires a small amount of area in each programmable logic block.

Abstract: Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.

Abstract: Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

Abstract: Circuits that have programmable parallel on-chip termination impedance are provided. On-chip transistors provide parallel termination impedance to an I/O pin. The impedance of the on-chip transistors can be programmed by an impedance matching circuit in response to the value of external resistors. The impedance matching circuit can regulate the impedance of termination transistors that are coupled to numerous I/O pins on an integrated circuit. This technique eliminates the need for external resistors that provide parallel termination impedance to I/O pins.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.

Abstract: Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.

Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.

Abstract: High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.

Abstract: A CMOS low noise band gap reference circuit outputs a substantially constant reference voltage VREF. The band gap reference circuit has an amplifier that includes a differential pair of bipolar junction transistors and a feedback circuit that adjusts its current to compensate for variations in the bias current through the circuit. The band gap reference circuit provides an output reference voltage VREF that is substantially constant over a range of temperature and a range of supply voltage.

Abstract: Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

Abstract: The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of different data to provide enhanced capabilities for the oximeter sensor. In addition to providing unique data to store in such a memory, the present invention describes unique uses of data stored in such a memory. The data stored in the memory chip includes data that can be used by an oximeter to determine if the sensor is adequately attached to the patient, data that indicates sensor assembly characteristics that can be used to correct for variations in optical efficiency, data that can provide compensation for infrared wavelength shifts caused by optical fiber, data relating to additional LEDs in the sensor, data indicating the last time the sensor was moved or disconnected, and data indicating whether the sensor is isolated.

Abstract: The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of different data to provide enhanced capabilities for the oximeter sensor. In addition to providing unique data to store in such a memory, the invention describes unique uses of data stored in such a memory. The data stored in the memory chip may include information relating to use of the oximeter sensor. For example, the memory chip may encode a sensor model identification that can be displayed on a display screen when the sensor is connected to an oximeter monitor. The memory may also encode a range of operating parameters such as light levels over which the sensor can function or a maximum drive current. The operating parameters are read and interpreted by a controller circuit to control the pulse oximetry system.

Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

Abstract: The present invention provides a memory chip for use in an oximeter sensor, or an associated adapter or connector circuit. The memory chip allows the storing of sensor expiration data to provide enhanced capabilities for the oximeter sensor. In addition to providing unique data to store in such a memory, the invention describes unique uses of sensor expiration data stored in such a memory.

Abstract: The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors.

Abstract: A controller architecture optimized for processing audio and video information in playback systems used for reproducing information stored on optical discs such as CDs and DVDs. The controller uses a unique parallel interface to facilitate the transfer of CD data and DVD data from the controller to a MPEG decoder. The controller also performs servo control operations, data processing and error detection and correction operations for CD data and DVD data, and provides shared memory resources for internal operations of the controller. DVD/CD playback systems incorporating the present invention occupy less real estate, have smaller pin counts, are less complex, and are cheaper to manufacture than conventional playback systems.