Abstract: A voltage translator uses an n-channel translator transistor to translate an input voltage at its drain to an output voltage at its source. The gate and substrate of the translator transistor are each biased by charge pumps. A reference transistor is also biased by the charge pumps. A reference input voltage is translated to a reference output voltage by the reference transistor. The reference output voltage is compared to a target output voltage by comparators. When the reference output voltage is below the target, the gate charge pump is turned on, raising the gate voltage to both the reference and translator transistors. The higher gate voltage VGATE raises the output voltage VOUT since VOUT=VGATE-VT for a transistor in saturation. When the reference output voltage is above the target, the substrate charge pump is turned on, pulling the substrate bias voltage below ground. The body effect causes the transistor threshold VT to increase as the substrate is pumped.

Abstract: A digital-versatile disk (DVD) controller interfaces to an AT bus using ATAPI commands delivered in command packets. A microcontroller executes firmware routines to control the servo that positions the read head, and reads data sectors from the DVD disk. The microcontroller also performs error correction on the DVD data in a disk buffer. A host state machine is used to interface to the AT bus. State transitions in the host state machine are enabled or blocked by the microcontroller by setting auto-transition bits in a state-control register. The microcontroller can set auto bits to allow the host state machine to automatically receive multi-byte command packets, or to transfer data or send status to the host without microcontroller intervention. The microcontroller also has the option of performing any of these steps manually, such as for more complex ATAPI commands. Overlapping ATAPI commands are allowed when the AT bus is released.

Abstract: A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers.

Abstract: A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM.

Abstract: A continuous-time filter is highly linear even when used with reduced 3-volt power supplies. In each stage of a multi-stage ladder network, resistor networks are attached to each input of a differential op amp. Each resistor network uses fixed resistors in series between the inputs and an intermediate node, and a fixed input resistor between the intermediate node and the op-amp input. The fixed input resistor improves linearity compared with a linear transistor. A transistor connects the internal node to ground, acting as a variable resistor to adjust the equivalent resistance of the resistor network. A control voltage applied to the gate of the transistor is generated by an analog control loop. The control voltage is the voltage input to a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL). The analog PLL control loop adjusts the control voltage and the resistance continuously as the filter operates.

Abstract: Frame acceleration is achieved by driving multiple LCD frames to a flat-panel display for each CRT frame. Rather than divide the flat-panel display into an upper and a lower half, the panel is divided into many segments. These are physical segments when the panel is row-addressable so that any segment can be accessed at any time. Virtual segments are used for standard dual-scan panels. A buffer memory receives gray-scale converted pixels and arranges them into segment-blocks. Multiple LCD frames are generated and stored using data acceleration. Frame-rate-cycling (FRC) of these multiple frames is used for gray-scaling. The size of the buffer memory is significantly reduced by organizing the frames into three or more segments since input and output timing can be overlapped, allowing lines to be sent to the panel at a higher rate than received by the buffer. While physical segments are most efficient, virtual segments still reduce memory requirements, especially when the multiple LCD frames are repeated.

Abstract: A content-addressable memory (CAM) cell isolates the gate nodes of pass transistors during a write operation. Select transistors between the word line and the pass-transistor gates are driven high by a column-select signal. The bit lines are precharged low. The word line is driven high to Vcc, and the select transistors drive the pass-transistor gates to Vcc-Vtn. One of the bit lines is then driven high to Vcc while the other bit line is held low. As the bit line swings high, capacitive coupling drives one of the pass-transistor gate nodes higher, above Vcc-Vtn. The select transistor then isolates the gate node from the word line. As the bit line continues to swing high, more coupling drives the gate node above Vcc. The boosted gate-node voltage increases the current drive of the pass transistor, accelerating the write operation. When the word line drop to ground, the select transistors drain the gate nodes, disabling the pass transistors and dynamically storing charge on the gates of storage transistors.

Abstract: A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor.

Abstract: A digital-to-analog converter (DAC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.

Abstract: The amount of time that a row of pixels in a flat-panel display is illuminated is modulated from frame-to-frame and from row-to-row. Pixels in rows that are on for a longer period of time appear brighter than pixels in rows that are on for shorter periods of time. Such line modulation is combined with frame-rate-cycling (FRC) to dramatically increase the number of gray scales that can be generated for any given number of frames in a FRC cycle, and with phase-offsetting to keep the frame period constant and to reduce flicker. An N-frame FRC cycle that previously generated N+1 gray scales now produces a full 2.sup.N gray scales. The total pixel-on time over the N frame cycle depends not just on how many frames the pixel is on, but on which frames the pixel is on. Since each row in each frame in the FRC cycle is on for a different amount of time, aliasing of the frames is greatly lessened or no longer occurs. A line modulation buffer and speeding up the pixel clock to the panel allow for greater modulation.

Abstract: A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P.

Abstract: Arbitrary content-files on arbitrary computing platforms are enclosed by content-wrappers. The content-wrapper also binds searchable metadata that describes the content-files within the content-wrapper, as well as user-defined metadata. The metadata can include a title, author, date, and keywords that describe the content-file. The metadata provides searchable text for arbitrary content-files, including non-textual content-files such as graphics, audio, video, and multimedia content. Thus non-textual as well as textual data can be searched. The format of the original content-file is unimportant since the content-file is wholly embedded within the content-wrapper, or a reference (such as a URL) to the content is embedded within the content-wrapper. Content-wrappers can thus enclose any kind of file or even a data stream. Content-wrappers are designed for different computers and operating systems such as Microsoft-Windows-based PC's, UNIX workstations, and Apple Macintosh computers.

Abstract: A bus switch has an n-channel bus-switch transistor that connects an input-bus signal to an output bus. A gate protection circuit prevents undershoots on the inputs from coupling to the output when the bus switch isolates the buses. The gate of the bus-switch transistor is driven to ground during isolation mode. When a high-to-low transition of the input-bus signal is detected, a pulse generator generates a pulse. The pulse disconnects the gate from ground. A connecting n-channel transistor with its gate connected to ground connects the gate to the input-bus signal when the undershoot pulls the input-bus signal below ground. Internal circuitry is isolated from the below-ground gate by an isolating n-channel transistor that has its gate driven by the input-bus signal during the pulse. A substrate bias generator is used for N-well processes, but P-well processes use a well protection circuit. The P-well under the bus-switch transistor is disconnected from ground during the generated pulse.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A portable personal computer (PC) can be connected to a variety of different external CRT monitors. Configuration of each CRT monitor is performed by the graphics display driver software so that the user does not have to re-configure the graphics sub-system every time a different CRT monitor is connected. Auto-configuration of Plug-and-Play monitors occurs by reading configuration information from the monitor itself. For Windows 95, the Plug-and-Play drivers are used for auto-configuration, or for older operating systems the video BIOS display-data-channel functions is used. Older "legacy" CRT monitors that do not support Plug-and-Play are still auto-configured. The vertical refresh rate for each resolution is stored in a default register on the graphics controller chip. The vertical refresh rate from default register is copied to an active refresh-rate register when a legacy (non Plug-and-Play) monitor is detected.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the network card and a bus switch are in a powered down state. Although n-channel transistors are normally off when the power is off, p-channel transistors can conduct. The hot bus could be disturbed when the bus switch is first connected since the p-channel transistor conducts when its gate is powered down to zero volts. A p-n junction from the p-channel transistor's drain to its substrate can become forward biased, drawing current from the hot bus. These problems are avoided by an isolation circuit that operates without power from a power supply. Instead, a high voltage from the hot bus is routed to the gate of the p-channel transistor, keeping the p-channel transistor turned off during hot insertion.

Abstract: A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fog, and specular color components. The gradients for texture attributes are also generated and sent to the graphics accelerator. Both the graphics accelerator and the CPU software perform triangle edge and span walking in synchronization to each other. The CPU software walks the triangle to interpolate non-texture color and depth attributes, while the graphics accelerator walks the triangle to interpolate texture attributes. The graphics accelerator performs a non-linear perspective correction and reads a texture pixel from a texture map. The texture pixel is combined with a color pixel that is received from the CPU software interpolation of non-texture attributes.

Abstract: An improved change-detection tool detects only relevant changes within Internet web pages on the world-wide-web. Changes back to an earlier version of a web page are not relevant and do not cause the user to be notified. Only changes to a new, unique version of the web page generate a user notification. After the user finishes registering the web page by specifying the URL and the user's e-mail address, the change-detection tool periodically retrieves the web-page at the specified URL and generates a checksum or signature to determine when to send a notification to the user. Signatures from several older versions of the web page are stored in a history table. When a new signature for a re-fetched page matches the most-recent signature at the top of the stack in the history table, no change has occurred. When the new signature matched any of the older signatures in the history table, the detected change is not unique and notification is not made even though a change has occurred.

Abstract: A multimedia notebook or laptop personal computer (PC) has an enhanced audio system. An external audio controller in a docking station is connected to the laptop PC's audio system using a digital-audio link. The digital-audio link uses digital signals that have high noise immunity. The high noise immunity allows the digital-audio signals to be routed through the inexpensive docking connector, which has many other noisy, high-speed signals. Dedicated, expensive, noise-prone, and difficult-to-connect analog-audio connectors between the laptop PC and the docking station are eliminated. Analog-digital converter audio CODEC's are placed in both the docking station and in the laptop PC. A master mixer in the laptop PC mixes digital audio from the external audio controller in the docking station with digital audio from an external audio controller inside the laptop PC. The master mixer also connects to a zoom-video audio port and to an internal PCI bus for storing and retrieving audio clips.