Abstract: A change-detection web server automatically checks web-page documents for recent changes. The server retrieves and compares documents one or more times a week. The user is notified by electronic mail when a change is detected. The user registers a web-page document by submitting his e-mail address and the uniform-resource locator (URL) of the desired document. The document is fetched and the user can select text on the page of interest. Non-selected text is ignored; only changes in the selected text are reported back to the user. Thus changes to less relevant parts of the document are ignored. The document is divided into sections bounded by hyper-text markup-language (HTML) tags. A checksum is generated and stored for each HTML-bound section. Storage requirements are reduced since only checksums are stored rather than the original documents. During periodic comparisons a fresh copy of the document is retrieved, divided into HTML-bound sections and checksums generated for each section.

Abstract: An integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office. The line card contains analog line circuitry such as a ring generator, off-hook detector, D.C. current feed, and a single analog-digital (A/D) converter. The phone line carries a composite signal of both the high-frequency ADSL data and the low-frequency voice or plain-old-telephone-service (POTS) signal. Instead of using an analog frequency-splitter with bulky, expensive inductor coils, a digital splitter is used. A digital-signal processor (DSP) can be used to perform the digital splitting of ADSL and POTS. The waveforms from the analog phone line are first converted to digital values by the A/D converter, and then a digital splitter separates the low-frequency POTS from the high-frequency ADSL.

Abstract: A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instructions are sent to the floating point pipeline near the end of the integer pipeline to allow the integer pipeline to fetch memory operands for the floating point pipeline. Thus the floating point pipeline relies on the memory operand fetch facilities of the integer pipeline. Complex CISC fetch-operate instructions pass through the integer pipeline first to fetch a floating point operand, and then begin the floating point pipeline for execution of a floating point operation. However, RISC instructions only use register operands and can begin the floating point pipeline earlier, reducing latency until the floating point result is produced.

Abstract: A differential-output current driver is constructed entirely of CMOS transistors. Pseudo-ECL levels are reached when a standard resistive termination is connected to the outputs. The current driver can also drive a non-standard termination to the PECL levels. The non-standard termination is low power because it does not draw standby current from power to ground. Current from the current sources within the current driver are assigned to either the switching current or the constant current. The constant current is applied directly to the outputs to drive the termination to a bias point. The switching current is applied to a differential pair of transistors which switch the switching current to one or the other of the differential outputs in response to a differential input. The constant current is combined with any switching current output from the differential transistors and applied to the differential outputs to drive the external termination.

Abstract: A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.

Abstract: Data is compressed in an industry-standard local-area network (LAN) such as IEEE 802.2 or 802.3. Compression occurs at a low level, in the data link layer just above the physical layer. The data in the packet is compressed, but the source and destination addresses are not compressed. A type/length field which indicates the length of the data field is adjusted for the new compressed length, while a frame checksum which was calculated for the uncompressed data is re-generated for the compressed data. Thus the packet with the compressed data has the length and checksum adjusted for the newly compressed data so that the packet appears normal to other layers of the LAN protocol. A status byte may be added to the compressed data to disable compression on a remote LAN station. The compressed data packet is compatible with hubs to other LANs and bridges to WANs.

Abstract: A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Abstract: A bus switch is constructed from an n-channel transistor. The gate terminal of the n-channel transistor is boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pulse is generated to drive the boosted node from ground to Vcc. The boosted node is also an input of a delay line. After a delay through the delay line, the pulsed pull-up is turned off. Feeding the boosted node to the delay line allows the pulse to be self-timed. The delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage. This leaker transistor is connected to a charge pump, and the delay line that enables this keeper transistor is also connected to the charge pump.

Abstract: A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips.

Abstract: A micro-relay replaces electromechanical and solid-state opto-isolated relays in a computer network. The micro relay is an integrated circuit containing several bus switches in parallel. Each bus switch can make or break a connection. The bus switch is an n-channel MOS transistor with the source and drain connected to different network busses. A bus enable input causes the connection to be made or broken. The bus enable input is separately buffered for each gate of each MOS transistor to prevent crosstalk between bus switches. Since the MOS transistor stops conducting when the source is at a voltage level of the power-supply voltage minus the threshold voltage, a boosted voltage is applied to the gate of the MOS transistor to allow conduction even when the source is at the power-supply voltage level. The boosted voltage is generated by a charge pump. A substrate bias is applied to the transistors to prevent crosstalk from undershoots.

Abstract: A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is loaded with a copy of the first few bytes of the second instruction to be dispatched in a cycle. In the previous cycle this secondary instruction buffer is used to determine the length of the second instruction dispatched in that previous cycle. That second instruction's length is then used to extract the first bytes of the third instruction, and its length is also determined. The first bytes of the fourth instruction are then located. When both the first and the second instructions are dispatched, the secondary buffer is loaded with the bytes from the fourth instruction. If only the first instruction is dispatched, then the secondary buffer is loaded with the first bytes of the third instruction. Thus the secondary buffer is always loaded with the starting bytes of undispatched instructions.

Abstract: A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width address components such as 16-bit address components which are effectively added together in modulo 64K. The other inputs receive full-width address components such as 32-bit components which are added in the full modulus, 4G. Reduced-width components are zero-extended to 32 bits before input to a standard 32-bit adder. A 16-bit carry generator also receives the reduced-width components and generates the carries out of the 16th bit position. When one or more carries is detected, a correction term is subtracted from the initial sum which is recirculated to the adder's input in a subsequent step. The correction term is the number of carries out of the 16th bit position multiplied by 64K.

Abstract: A graphics controller drives a flat-panel display and simultaneously drives an external cathode-ray-tube (CRT) display. Horizontal clock pulses continue to be applied to the flat panel during the CRT's vertical blanking or re-trace period so that the flat panel is not left in a constant state during the entire re-trace period. Leaving the flat panel in a constant state for a long period of time can cause flicker or delayed response immediately after the re-trace period ends. Running the horizontal clocks during the re-trace period can lead to D.C. buildup or rolling flicker, believed to be caused by a polarity-inversion counter in the panel assembly which is not designed to receive additional horizontal clocks beyond the number of lines on the flat panel. D.C. buildup in the flat panel is reduced by adding a high-frequency burst of horizontal clock pulses to the flat panel during the CRT's vertical re-trace period. The burst of clock pulses adjusts the count in the polarity-inversion counter.

Abstract: The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not checked with the first instruction's destination. Instead, instructions with destination-destination dependencies are dispatched together as a group. These instructions flow down the pipelines. At the end of the pipelines the destinations are compared. If the destinations match then the results are merged together and written to the register. When instructions write to only a portion of the register, merging ensures that the correct portions of the register are written by the appropriate instructions in the group. Thus older code which performs partial-register writes can benefit from superscalar processing by dispatching the instructions together as a group and then merging the writes together at the end of the pipelines.

Abstract: A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slave caches, freeing the slaves of these bandwidth-robbing duties. Only the slave caches store sub-line valid bits with all cache lines; the master cache has only full cache lines valid. During a miss from a slave cache, the slave cache sends its sub-line valid bits to the master cache. The slave's sub-line valid bits are loaded into a request pipeline in the master cache. As requests are fulfilled and finish the pipeline, its address is compared to the addresses of all other pending requests in the master's pipeline. If another pending request matches the slave's index and tag, its sub-line valid bits are updated by setting the corresponding sub-line valid bit for the completing request's sub-line.

Abstract: A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon reset, and performs various system checks and memory allocation. A special emulation driver is loaded into a portion of main memory set aside at reset. Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory. A TLB is enabled, and translation tables and drivers are set up in the emulation memory. All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode. Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory.

Abstract: A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions.

Abstract: A multi-node server transmits world-wide-web pages to network-based browser clients. A load balancer receives all requests from clients because they use a virtual address for the entire site. The load balancer makes a connection with the client and waits for the URL from the client. The URL specifies the requested resource. The load balancer waits to perform load balancing until after the location of the requested resource is known. The connection and URL request are passed from the load balancer to a second node having the requested resource. The load balancer re-plays the initial connection packet sequence to the second node, but modifies the address to that for the second node. The network software is modified to generate the physical network address of the second node, but then changes the destination address back to the virtual address. The second node transmits the requested resource directly to the client, with the virtual address as its source.

Abstract: The timing of control signals in a parallel port is measured and adjusted to achieve optimum timing of these control signals. At boot-up, a routine writes alternating data to the control register of the parallel port. The control register drives control signal over a parallel-port cable to an external parallel-port device connected to the parallel port of a personal computer (PC). Transitions of the control signal trigger an external timer in the external parallel-port device which measures the pulse width of the control signal. The measured pulse width is sent back to the PC over the parallel cable and compared to a target pulse width. When the measured pulse width is less than the target, additional intervening instructions are inserted between writes to the parallel-port control register. The intervening instructions are a simple delay loop. Alternately the internal timer on the PC may be used. Since the accuracy is less for the internal timer, many IO writes are performed to average out errors.

Abstract: A graphics controller has a standard RGB graphics pixel path from a graphics memory. A second path from the graphics memory transfers movie-overlay pixels in YUV format. Two pixel muxes are used. Each pixel mux selects either RGB graphics pixels or YUV movie pixels converted to the RGB color space. A first pixel mux loads either the graphics or the movie pixels to a path to the external CRT. A second pixel mux loads either the graphics or the movie pixels to an LCD path leading to a flat-panel LCD display. The pixel muxes can act in unison to display the same image on both the external CRT and the local LCD panel, and the movie pixels may be overlaid as a small window over the graphics data. The pixel muxes can also act separately so that different images are displayed on the external CRT and the local LCD panel. One pixel mux selects the RGB pixels while the other pixel mux selects the converted YUV pixels.