Abstract: A universal cable connects a personal computer's parallel port or PCMCIA socket to a variety of types of external peripheral devices. The universal cable contains a translator circuit that converts signals from the parallel port or PCMCIA socket to external interface signals. The translator circuit combines together bytes from the parallel port to out put words when the external peripheral is an IDE or ATAPI device, or a subset of the ISA or AT bus. The translator circuit passes bytes through to 8-bit SCSI peripherals. The 16 data bits from the PCMCIA socket are passed through to IDE, ATAPI, and ISA devices, but split into bytes for SCSI devices. General-purpose I/O for external peripherals is also supported using separate input and output signals rather than bi-directional I/O. Software on the personal computer controls the configuration of the translator circuit, allowing the universal cable to be re-configured for different types of external peripherals.

Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.

Abstract: A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block.

Abstract: Pulp-insulated telephone cables common in Japan and other countries have higher cross-talk interference than plastic-insulated cables common in the United States. Deployment of newer xDSL systems in Japan has been limited by the high cross-talk interference in those pulp cables, especially the near-end cross-talk (NEXT) from ISDN services using time-compression multiplexing (TCM). A TCM-DSL that can share pulp-cable bundles with TCM ISDN lines eliminates the NEXT interference by synchronizing transmission and reception with the TCM ISDN equipment for the same cable bundle. The TCM-DSL line uses TCM that is synchronized with the ISDN transmit and receive windows so that the TCM-DSL is transmitting but not receiving when the ISDN modems at the same side are transmitting. When ISDN at the same side are receiving and not transmitting, NEXT interference does not exist. Thus higher-speed TCM-DSL data can be received during the ISDN receive windows with reduced interference.

Abstract: A change-detection tool detects significant changes in numerical fields within internet web pages on the world-wide-web. A user identifies web-page web pages by specifying the web page's URL. The user then highlights one or more numeric fields on the web-page web page. The numeric fields' values are extracted to cells on a spreadsheet displayed to the user. The user enters parameters and formulas into unused spreadsheet cells. The formulas operate on the numeric values extracted from the web page to the spreadsheet's cells. The user also enters notification limits or conditions that are based on the results of the formulas. The notification conditions indicate when a change notification is to be e-mailed to the user. After the user finishes registering the web-page web page, the change-detection tool periodically retrieves the web-page web page at the specified URL and re-calculates the formulas and determines if the notification conditions have been met.

Abstract: A distributed-client change-detection tool detects changes in Internet web-page documents on the world-wide-web. To register a web page for change detection with a change-detection server, a user specifies the web page's URL. A client-side change-detection application is downloaded to the user's client from the change-detection server. The server assigns a date and time for the client to perform change detection. At the assigned time and date, the client fetches a new copy of the web page and compares it to an archived copy to detect changes. When the client detects a change, it sends a notification with the URL to the server. The server verifies that the change has not already been reported by another user's client and then notifies all users of the registered web page. As more users are registered for a web page, change detection is performed more frequently. The most popular pages with tens of thousands of registered users are checked every few minutes.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver transistor. Both transistors drive the output low in parallel initially during a voltage transition, but the larger transistor is disabled for the remainder of the output voltage swing when reflections and ringing occur. A pulse is generated by a transition detector when an input to the output buffer transitions low. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. A Resistor in series with the smaller driver transistor absorbs these reflections.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host.

Abstract: An n-channel bus switch has a transistor gate boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. No pulse generator is needed. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pullup transistor drives the boosted node from ground to Vcc. The pulse generator is eliminated by using a Schmidt-trigger to sense the voltage of the boosted node. Once the Schmidt-trigger senses that the voltage of the boosted node is near Vcc, the pull-up is turned off. A delay line first drives the gate of the pullup transistor to a threshold below Vcc using an n-channel pullup, and then drives the gate to Vpp using a p-channel pullup. A delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage.

Abstract: A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons.

Abstract: A video-input stream to a personal computer (PC) is converted from YUV format to RGB format. Two look-up tables are used. One look-up table has the Y and V components as address inputs, while the other look-up table has Y and U components as address inputs. The address inputs select one data word in the table for the Y,V or Y,U pair. Each data word contains an exact conversion to either the red component R or the blue component B since the result of the functions R=Y+1.371*V is stored in one table while the result of the function B=Y+1.732*U is stored in the other table. Each table also contains a partial green component in each data word. The Y,U table contains the result of the partial-green function (Y/2-0.698*V) in each data word, while the other table contains the result of the partial-green function (Y/2-0.336*U). An adder adds the two partial-green results from the two tables to produce the green component G.

Abstract: A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards.

Abstract: A distributed client-server application is modified while running. The application is not stopped so that updating of objects is transparent. A meta server catalogs all object classes for both the server and the clients. Modifications are specified by a run-time update tool and converted to change commands. The meta server receives the change commands and updates the structure of an application database. Object class definitions are read from the meta server and modified by the meta server to access the new structure of the application database. The modified object-class definitions are written back to persistent storage for the meta server, and compiled and linked to form new object classes. An object adaptor receives a list of modified object classes from the meta server and notifies all server and client caches of the object classes on the list. The obselete objects are invalidated by the caches and new objects are created using the most up-to-date class definitions.

Abstract: Audio sample rates are converted by an arbitrary ratio of Q/P using a two-stage sample-rate converter. One stage is an L-tap low-pass finite-impulse-response (FIR) filter, while the other stage is a linear interpolator. Coefficient storage for the L-tap low-pass FIR filter is dramatically reduced by reducing the effective P factor. The effective P factor is reduced by using two stages, with each stage adjusting the sampling rate by a different ratio. A first stage adjusts the sampling rate by Q0/P0, while a second stage further adjusts the sampling rate by Q1/P1. Q0 and P0 are large integers of about 400 to 700 that differ by one or three; thus the ratio Q0/P0 is very close to one. The linear interpolator stage eliminates or adds one or three samples and smoothes the samples by linear interpolation over the 400 to 700 remaining samples. The FIR filter stage adjusts the sample rate by a ratio of Q1/P1, which is approximately but not exactly Q/P.

Abstract: An external hard disk is connected to a personal computer (PC) through the parallel port. A parallel-port expansion card is installed on the AT bus in the PC for communicating with the external hard disk. The parallel-port expansion card has a ROM containing intercept code. The address of the ROM is automatically configured when the system BIOS scans for expansion ROMs during booting. When no other ROM drives the data bus when an address is scanned, the parallel-port card latches the address and has the ROM drive its data onto the bus. Future accesses to the latched address access the ROM. The ROM's code replaces the interrupt table's starting address of the hard-disk-controller routine with the address of an intercept routine. All hard-disk operations using the interrupt first execute the intercept routine. The intercept routine copies any data writes to the external disk. Thus the external disk has a redundant copy of the PC's internal hard disk.

Abstract: An audio special-effect is created by a slow phase shift. A series of all-pass digital filters are used to shift the phase of an input stream of digital-audio samples. The amount of phase shift is determined by filter coefficients. The filter coefficients are increased and decreased to sweep the phase shift up and down over a relatively long period of time such as one second per sweep. The filter coefficients must be continuously re-generated by a processor as each sweep occurs. Coefficient generation loads the processor, reducing performance of other programs and user applications. An exact prior-art method requires a division operation for each coefficient generated. Since division operations are slow, the processor is especially burdened by coefficient generation. An approximate method for coefficient generation eliminates the division operation and instead uses a multiply or a simpler shift operation.

Abstract: A hardware-based emulator is partitioned onto two boards. An emulation board has field-programmable gate array (FPGA) chips mounted on a top surface, and connection posts protruding through to the bottom surface. The I/O pins of the FPGA chips that carry emulated signals are connected to the connection posts but not directly to other FPGA chips on the emulation board. An interconnection board has a grid of wire-wrap posts. The tops of the wire wrap-posts mate with the connection posts when the emulation board is plugged in to the interconnection board. The wire-wrap posts extend through the interconnection board and out the bottom surface. Interconnection is made by wire-wrap wires wound around the wire-wrap posts. Thus interconnection between FPGA chips on the emulation board is made by wire-wrap on the interconnection board, while the logic gates are emulated in the FPGA chips on the separate emulation board.

Abstract: A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed.