Abstract: A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

Abstract: A buffer or driver circuit drives a high-capacitance clock signal line inside an integrated circuit (IC). Power is reduced by limiting the voltage swing of the clock output. The clock voltage swing is limited to within a transistor threshold-voltage of power and ground by feeding the output voltage back to the gates of the driver transistors which drive the output clock signal line. Thus the output clock swings from Vtn to Vcc-.vertline.Vtp.vertline. rather than from ground to Vcc. The limited output swing reduces dynamic power which is more critical than static power in downstream logic receiving the clock for higher-speed clocks. Crowbar current from power to ground through the driver transistors is eliminated by turning off the active driver transistor before the complementary driver is turned on. The gates of the driver transistors are charged and discharged from the clock line capacitance rather than from power and ground.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: An embedded ROM has a column of static RAM cells attached to the end of the row lines. When a row of ROM cells is activated by the row line, a RAM cell is also activated by the row line. The RAM cell indicates if the data in the selected row's ROM cells is valid. When the RAM cell indicates that the ROM data is not valid, external memory is read to obtain a patched instruction and the ROM data is ignored. The ROM's base address is translated to a base address in external memory of patch code. The ROM's offset address is used as the offset into the patch-code region of external memory. Thus address translation is minimal as the offset is not translated. A single ROM instruction can be updated by a single patch instruction in external memory, providing fine granularity of code updates. Longer update routines can be located in a patch-code overflow region of external memory.

Abstract: A graphics controller overlays a movie window over the graphics pixel data. Movie pixels are from a movie source and are muxed into the pixel path by a pixel mux near the end of the graphics pipeline. A comparison of the current pixel count to the pixel address of the start and ending boundaries of the movie window controls the pixel mux, which selects either graphics pixels or movie pixels for display to a screen. Since the graphics controller is pipelined, the pixel compare near the end of the pipeline does not restart the graphics pipeline early enough for it to pre-process the graphics pixels. The graphics pipeline does not stop during the movie window but instead performs dummy fetches from the graphics memory to a CRT FIFO in the graphics pipeline. Dummy fetches are fetches of graphics pixels that are not displayed. Since these fetches contain non-displayed pixels, they are not needed except to keep the fetch count counting even during the movie window.

Abstract: A processor has an execution unit that includes an arithmetic-logic-unit (ALU). Logic instructions are executed by a Boolean logic unit constructed around a 4:1 vectored mux. For Boolean logic instructions, the two operands are applied to the select control inputs of the vectored mux, while truth-table signals representing a truth-table for the Boolean operation being executed are applied to the data inputs of the vectored mux. Sign-extension of one of the operands can be performed by modifying the truth-table signals for an upper portion where the sign-extension occurs. Merge instructions are also executed on the vectored mux by reversing the connection of the operands to the vectored mux. The operands are applied to the select control inputs of the vectored mux for Boolean operations, but applied to the data inputs for merge operations. A mask is generated and applied to the select control inputs to select the correct portions of the first and second operands to generate the result of the merge operation.

Abstract: Memory requests from multiple processors are re-ordered to maximize DRAM row hits and minimize row misses. Requests are loaded into a request queue and simultaneously decoded to determine the DRAM bank of the request. The last row address of the decoded DRAM bank is compared to the row address of the new request and a row-hit bit is set in the request queue if the row addresses match. The bank's state machine is consulted to determine if RAS is low or high, and a RAS-low bit in the request queue is set if RAS is low and the row still open. A row counter is reset for every new access but is incremented with a slow clock while the row is open but not being accessed. After a predetermined count, the row is considered "stale". A stale-row bit in the request queue is set if the decoded bank has a stale row. A request prioritizer reviews requests in the request queue and processes row-hit requests first, then row misses which are to a stale row.

Abstract: A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When 3 CPU's are on the die, their outputs are compared during a self-testing mode. If outputs from all three CPU's match, then no error is detected. When two CPU's outputs match, but a third CPU's output mismatches, then the third CPU is faulty. The output compared from each CPU is a serial scan-chain shift-out, parity from internal test points, and a result written to the shared cache. Each CPU core has a serial scan chain. The serial scan chain strings together most flip-flops in the CPU core into a serial chain. A test clock is pulsed to shift out the data from these flip-flops. During each test clock period, the serial data from each CPU is compared to the serial data from other CPU's. Internal test points within each CPU core are defined at high traffic areas in the pipeline.

Abstract: A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage.

Abstract: A network switch uses a simple switch core of analog MOS transistor switches. The switch core is surrounded by many media-access controllers (MAC's) which buffer the data through the switch core. Multiple connections through the switch core may be made between different pairs of MAC's. Just one signal path through the switch core is needed per connection as a second path through the switch core for the clock is not needed. The clock is not encoded with the data, so PLL's are not needed for clock recovery. Data skew is instead measured for each packet transmitted through the switch core. A start flag is added to the packet by a source MAC as a packet header before being transmitted through the switch core. The start flag is a unique sequence which is detected by the destination MAC and triggers measurement of the data skew of the received start flag to the local clock. The measured data skew is then used to compensate for the rest of the packet.

Abstract: A CMOS output buffer has a first stage with smaller driver transistors and a second stage having larger driver transistors. Both stages drive the output in parallel during the first half of a voltage transition, but the larger, second stage is disabled during the second half of the output voltage swing. The output voltage is fed back to an isolation circuit by a pulse generator which is triggered by the output reaching the switching threshold. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. Resistors in the smaller first stage absorb these reflections.

Abstract: A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage.

Abstract: A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slave caches, freeing the slaves of these bandwidth-robbing duties. The master cache has a tag pipeline for accessing the tag RAM array, and a data pipeline for accessing the data RAM array. The tag pipeline is optimized for fast access of the tag RAM array, while the data pipeline is optimized for overall data transfer bandwidth. The tag pipeline and the data pipeline are bound together for retrieving the first sub-line of a new miss from the slave cache. Subsequent sub-lines only use the data pipeline, freeing the tag pipeline for other operations. Bus snoops and cache management operations can use just the tag pipeline without impacting data bandwidth.

Abstract: A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack pointer is needed for generating the stack-top address in memory. The stack-top address is generated early in the pipeline. Other stack instructions in the pipeline which have not yet incremented the stack pointer are located with a stack valid bit array. The stack valid array indicates the increment or decrement amounts for stack instructions in each pipeline stage. An overall displacement or increment value is computed as the sum of all increments and decrements for stack instructions in the pipeline which have not yet updated the stack pointer. The overall displacement which accounts for all unfinished stack instructions is added to the stack pointer from the register file to generate the stack-top address.

Abstract: A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions.

Abstract: A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these breakpoints is loaded into the single breakpoint register on the CPU. When a translation-lookaside buffer (TLB) on the CPU detects a page miss, a page miss handler activates a debug processing routine to determine if the faulting page contains one of the breakpoints. If the faulting page does contain a breakpoint, then this breakpoint is written to the single breakpoint register on the CPU. Any page in TLB is invalidated if it contained the old breakpoint that was overwritten by the new breakpoint in the single breakpoint register. Thus only one breakpoint can have a page translation in the TLB at any time, and the breakpoints are swapped in and out of single breakpoint register when the TLB entries are swapped. A TLB invalidate entry instruction finds the old breakpoint's TLB entry and invalidates it.

Abstract: A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor table and an active segment descriptor cache. The active segment descriptor cache holds a copy of the segment descriptors for the active segments in a central processing unit (CPU). The active segment descriptor cache also hold the first and last clear page numbers and the first and last linear address offsets for the active segment. A software segment load routine copies portions of the segment descriptor from the segment descriptor table to the active segment descriptor cache when a user program loads a new segment. Only the segment base address is copied to the CPU die; the segment limit and selector need not be stored on the CPU die.

Abstract: A master-slave cache system has a large master cache and smaller slave caches, including a slave data cache for supplying operands to an execution pipeline of a processor. The master cache performs all cache coherency operations, freeing the slaves to supply the processor's pipelines at their maximum bandwidth. A store queue is shared between the master cache and the slave data cache. Store data from the processor's execute pipeline is written from the store queue directly into both the master cache and the slave data cache, eliminating the need for the slave data cache to write data back to the master cache. Additionally, fill data from the master cache to the slave data cache is first written to the store queue. This fill data is available for use while in the store queue because the store queue acts as an extension to the slave data cache. Cache operations, diagnostic stores and TLB entries are also loaded into the store queue. A new store or line fill can be merged into an existing store queue entry.

Abstract: The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate generate and propagate signals within the adder. The adder has a first stage that reduces each bit-position to a generate and a propagate signal. The adder's second stage propagates the carries in the adder using these generate and propagate signals to generate the sum. Thus the adder's first-stage logic is also used for the leading one/zero prediction, reducing cost and complexity. An ECL half-adder cell is preferably used for the adder's first stage. A zero output is added to the ECL half-adder cell at minimal cost. The shift for the leading one/zero prediction is accomplished in two stages, with a selective complement of negative sums between the two-stage shift.

Abstract: A stack-register swap or exchange instruction is executed by splitting the exchange into two halves, and then each half is absorbed into a surrounding instruction by translating its source or destination operands. If one or both surrounding instructions are absent, then one or both halves of the exchange instruction are inserted into the pipeline as separate pipeline flows. When the surrounding instructions are stack-based, the stack operands are first converted to a destination and two source operands that specify a register by absolute number. A translation circuit then translates one of the operands of a surrounding instruction so the surrounding instruction's source is read from the exchange instruction's source, or so that the surrounding instruction's destination is written to the exchange instruction's destination, eliminating the need for processing a separate exchange instruction.