Abstract: An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage.

Abstract: A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state.

Abstract: A content-addressable memory (CAM) cell uses only n-channel (NMOS) transistors. A total of six transistors (6T) are used in the cell. Dynamic storage and differential sensing are used. A pair of bit lines carry true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. The sources of the storage transistors are grounded. Charge is dynamically stored on the gates of the storage transistors when the pass transistors are turned off. One storage transistor has a gate charged to a high voltage and is thus on, while the other storage transistor has its gate discharged to a low voltage and is thus off. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. During a compare operation, the test data and its complement are applied to the bit lines, turning one of the match transistors on and the other off.

Abstract: Indexed registers in controller chips are read in a two-step process. First, an 8-bit write instruction writes an index into an index register in the controller chip. Secondly, a 16-bit read instruction reads both the index register and a data register selected by the index from the index register. When index registers are read in a multi-threaded system, programs in two different threads could access the same index register, each writing a different index into the index register. When another thread over-writes an index written by a current thread, the wrong index and the wrong data are read by the current thread. The current thread detects that the index was overwritten by another thread by extracting the index from the 16-bit read and comparing it to the desired index. When the extracted index mis-matches, the current thread retries, again writing the index and reading back both the index and data.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: An output buffer for a line driver uses transmission gates for active termination. A large p-channel driver is pulsed on during a low-to-high output transition, but this driver is turned off once the output voltage reaches a threshold. A feedback circuit includes a sensing inverter that has its input connected to the output node. The sensing inverter causes the gate of the p-channel driver to be driven high once the output swings past the threshold. A similar n-channel driver transistor is pulsed on during a low-going output transition but is disabled by a feedback circuit that senses the output voltage falling below a threshold. A pullup transmission gate is also connected between the output and the power supply, while a pulldown transmission gate is connected between the output and ground. Each transmission gate contains a p-channel and a n-channel transistor in parallel.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: A client-side dispatcher resides on a client machine below high-level client applications and TCP/IP layers. The client-side dispatcher performs TCP state migration to relocate the client-server TCP connection to a new server by storing packets locally and later altering them before transmission. The client-side dispatcher operates in several modes. In an error-recovery mode, when a server fails, error packets from the server are intercepted by the client-side dispatcher. Stored connection packet's destination addresses are changed to an address of a relocated server. The altered packets then establish a connection with the relocated server. Source addresses of packets from the server are changed to that of the original server that crashed so that the client application is not aware of the error. In a delayed URL-based dispatch mode, the client-side dispatcher intercepts connection packets before they are sent over the network.

Abstract: Memory modules such as SIMMs and DIMMs are automatically tested by a target-system motherboard such as a PC motherboard. An automated SIMM/DIMM handler is connected to a handler adaptor board that is mounted to the back or solder-side of the PC motherboard. The relatively flat surface of the solder-side of the PC motherboard allows close mounting of the handler. One or more of the SIMM sockets on the motherboard is removed to provide mounting holes for the handler adaptor board. The handler adaptor board provides electrical connection from the module-under-test (MUT) in the handler to the removed SIMM socket on the PC motherboard. The handler adaptor board provides a slight spacing or offset from the solder-side surface of the PC motherboard's substrate, allowing the handler to be plugged directly into tester-connectors on the handler adaptor board.

Abstract: A fully duplex cordless telephone has a transmitter and a receiver connected to a common antenna. A broad-band antenna coupler such as a ferrite-core hybrid transformer may replace a more costly duplexer with filters. Since all characteristics of the transmit signal are known, the transmit signal removes itself from the receiver by signal cancellation. The canceling signal is extracted from the composite signal from within the receiver front end, after the antenna coupler and low noise amplifier. This composite signal is coupled to the first input of a difference amplifier, and the output of this amplifier is coupled to the remainder of the receiver. The composite signal is coupled to the second input, after its smaller receive component has been further suppressed, and its remaining transmit signal has been adjusted by two feedback control systems to restore its phase and amplitude to be equal to the transmit component of the composite signal.

Abstract: An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes.

Abstract: A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded DRAM memory. The memory block has rows and columns. Data read from a DVD optical disk is read in row order. Rather than write the DVD data across the rows in the memory block, the DVD data is accumulated into 16-byte words, and successive 16-byte words are written down a column in the memory block. Each row from the DVD disk is written to a 16-byte-wide column in the memory block. The embedded DRAM has a wide 16-byte interface, so all 16 bytes in a word are written during a single memory-access cycle. All the bytes in the memory block must be read in column-order for column-syndrome generation. Since the row-column ordering is reversed, the column-syndrome generator reads bytes across the memory-block rows. Most of these fetches are DRAM page hits, so access speed is improved for column-syndrome generation.

Abstract: Low-latency arbitration is provided for a super-priority communications device such as modems and ISDN/DSL routers, LAN switches and routers. Phantom arbitration slots are inserted between each pair of permanent slots. When a request from the super-priority agent is received, the next phantom slot is used to service the request. The initial latency is just one slot period rather than the whole arbitration loop. Other phantom slots are skipped until the same phantom slot is again activated at the same point in the arbitration loop during subsequent rounds of arbitration. Thus only the initial latency is reduced; subsequent requests from the super-priority agent are handled just once for each arbitration cycle. The low initial latency allows the communications device to quickly respond to an incoming call. Other real-time agents are assigned a fixed slot in a round-robin arbitration. The last arbitration slot is used by all non-real-time agents.

Abstract: A digital-to-analog converter (DAC) uses switched capacitors summed, to an op amp to generate the analog output voltage. Least-significant-bits (LSBs) of the digital input switch a reference voltage to binary-weighted capacitors. The most-significant-bits (MSBs) are thermometer-coded and switch the reference voltage to capacitors that have a same size, double the size of the maximum LSB's capacitor. The thermometer-coded MSB's are scrambled before switching the same-size capacitors so that the assignment of a digital input bit to a capacitor varies from sample to sample. Any variation in capacitances for the same-size capacitors is thus spread to different digital values so that errors do not occur consistently for the same digital values. The scrambler uses radix-2 butterflies to swap bit assignments and thus outputs an even number of signals to the capacitors. Since the thermometer code is an odd number of signals, an extra signal is present that is always driven high or low.

Abstract: Low-level network services are provided by network-service-provider plugins. These plugins are controlled by an extensible service provider that is layered above the TCP layer but below the Winsock-2 library and API. The extensible service provider orders the plugins based on the function performed by each plugin and on ordering hints. Plugins that redirect the protocol or socket are executed first. Plugins that examine packets or block entire packets are executed before plugins that modify packets. Plugins that compress or encrypt data are executed last for outgoing packets. Ordering hints cause a plugin to be executed before or after others in its functional class. Ordering allows examining plugins that simply read data get to the packets before an encrypting or compressing plugin renders the data unreadable. The extensible service provider has a plugin manager that orders and controls execution of the plugins. A filter manager evaluates one or more packet-filters.

Abstract: A gate-array cell uses smaller and larger transistors. Four larger transistors are provided: two n-channel and two p-channel. A small p-channel transistor is placed between the contact tabs of the polysilicon lines of the two larger p-channel transistors, and between the p-channel transistors and a N-well tap. A small n-channel transistor is similarly placed between the contact tabs of polysilicon lines of the two larger n-channel transistors, and between the n-channel transistors and a P-well tap. The cell is slightly expanded in height to accommodate the two smaller transistors. The smaller transistors enable a reduction in the number of transistors required for latches and flip-flops. The smaller transistors allow a feedback inverter to directly connect to an input, since the input can easily over-power the feedback current. This is not possible for standard gate array cells having only one transistor size. Transmission gates are eliminated when direct feedback is feasible.

Abstract: Low-level network services are provided by network-service-provider plugins. These plugins are controlled by an extensible service provider that is layered above the TCP or other protocol layer but below the Winsock-2 library and API. Policy servers determine priority of network traffic through control points on a network. Examining packets passing through these control points provides limited data such as the source and destination IP address and TCP ports. Many applications on a client machine may use the same IP address and TCP ports, so packet examination is ineffective for prioritizing data from different applications on one client machine. Often some applications such as videoconferencing or data-entry for corporate sales are more important than other applications such as web browsing. A application-classifier plugin to the extensible service provider intercepts network traffic at above the client's TCP/IP stack and associates applications and users with network packets.

Abstract: A hybrid data parallel/serial data transfer system with phase adjustment and symbol coding for switching digital data packets in order to facilitate massive high speed transfer of information with a limited number of signal lines. Much higher data transfer is possible than in a conventional serial data transfer. Multi-giga bits or Tera bits can be transferred easily over a long distance using this invention. Data transmission apparatus is described in which data is transmitted over a communication link or trunk consisting of a plurality of lines. Each message is transmitted as a sequence of groups of data bits, the bits in each group being transmitted in parallel over the trunk. Each line or path carries a signal and each message is preceded by a serial start pattern. The receiver comprises a plurality of decoders for receiving data signals from the trunk. These signals are fed to a separate buffer. The contents of the buffer are then read out in parallel.

Abstract: A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch.

Abstract: An electro-static-discharge (ESD) protection circuit protects internal power supplies in a mixed-signal IC. An active protection circuit is used. The ESD-protection circuit uses standard transistors and is actively enabled and disabled by standard transistors. A standard thin-oxide NMOS transistor is the ESD switch (shunt) between power supply busses. This thin-oxide transistor ESD switch is actively enabled and disabled by a control circuit. NMOS transistors in the control circuit discharge the gate node of the ESD switch when the power supplies are powered up, thus actively disabling the ESD protection circuit. When an ESD pulse is applied to a supply when powered down, a capacitor couples the rapid voltage rise to the gate node. The rising voltage turns on the ESD switch, shunting the ESD pulse to the other supply. A resistor and a p-channel MOS transistor in series then discharge the gate node to the other supply. The capacitor, resistor, and p-channel transistor form an RC network.