Abstract: A method and apparatus is described for the checking of the correctness and consistency of units and dimensions of variables and constants used in expressions, such as those used in computer programs. The present invention relates to a method (200) and apparatus (100) for performing such checking. A set of user-supplied precompiler directives is added to the computer program that is to be checked. Broadly, functions, function parameters, constants and variables are replaced with strings from the precompiler directives. The resulting expressions are reduced into a standard form. The expressions in the reduced form are tested for homogeneity according to a set of predetermined conditions.

Abstract: A methodology and system allows a plurality of reward scheme owners to give differential rewards, through a plurality of reward distribution agents, to various users based on the user profile. The reward scheme owner may be a seller, a manufacturer, a sales promotion agent or even an intermediary. Similarly, the reward distribution agent may be an on-line or a physical retailer, a broker, a seller or an intermediary. Also the users may be consumers, businesses, brokers or other intermediaries. In one specific case, a reward scheme owner defines a plurality of reward schemes, including at least one differential reward scheme giving different rewards to different users. The reward scheme owner communicates these to a central reward scheme database server. The reward scheme owners may or may not advertise these schemes. The user visits an online or a physical store.

Abstract: A synchronous collaboration environment that supports real-time collaboration of multiple participants, each having shared and independent views of the shared workspace. Multiple views per participant are provided. Some of the views seen by a participant can be shared views with the usual common cursor and annotation tools. The shared views need not be homogeneous, which means that for a given view, each participant can see more than just some common data in his or window for the view. What the participant sees separately from the common data can make his or her shared view different from that of other participants. The view can be different due to different data being exposed in the view. Some of the views seen by a participant can be independent views. This allows to the participant synchronous working with the shared workspace alone on his or her own. The collaboration system includes a user interface and support for aligning views including goto and overlaying.

Abstract: A method, an apparatus, and a computer program product for reducing simulation time taken by a CPU during signal integrity analysis are disclosed. In the method, a circuit network is provided for similuation having a number of transistors. Preferably, the provided circuit network is an ANDAP, SPICE, or AS/X net. A simplified circuit network having a reduced number of transistors is generated from the provided circuit network. Transistors in the provided circuit network having the same channel length and being configured in parallel are replaced by a single transistor having corresponding aggregate characteristics for the replaced transistors. The provided circuit network is then simulated using the simplified circuit network.

Abstract: A method of keyless encryption of messages allows secure transmission of data where data security is not available for some technical or legal reason. The method of data transfer uses a challenge response in which a correct response to a challenge is used to transmit the value “1”, while a deliberately false response is made to transmit the value “0”. Any message can be transmitted as a binary string using successive applications of this method.

Abstract: A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch. However, no data-inverting circuit is included in either of the feedback paths. Advantageously, all the elements of the flip-flop may be constructed using MOSFET transistors implemented according to any one of a variety of semiconductor technologies. In more than one particularly advantageous embodiments, the flip-flop is constructed using a total of twelve transistors.

Abstract: A methodology of highly interactive intra-object relevance feedback is used to retrieve multimedia data from a database. The query object could consist of one or more images, images derived from video, a video sequence, or an audio clip. The query is adjusted using the information fed-back by the user about the relevance of previously extracted part(s) from the object itself, such that the adjusted query is a better approximation to the user's perception. The information fed-back by the user during intra-query modification is used for intra-object learning of the user's perception. The refined query is subsequently used for inter-object relevance feedback where data is retrieved from the database based on parameters learnt by intra-query object feedback mechanism, and the user provides feedback by ranking the retrieved objects in order of their relevance to him or her.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.A novel process of forming vertical (e.g.

Abstract: A full wafer packing technique for semiconductor devices is provided. The semiconductor wafer is mounted on a substrate wherein the coefficient of thermal expansion of the substrate is matched to that of the wafer. The wafer is also provided with at least one bus member extending across the surface of the wafer to provide voltage power to the devices. Further, the packaging includes a cover, and a solid dielectric thermally conducting material which is disposed between and the wafer and substrate and fills the space between the cover and wafer and substrate.

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lighography, per se, is formed.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting to resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.

Abstract: Disclosed is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout layer having an opening in correspondence with the portion of the would-be silicon mesa where a channel stop is desired is formed. N type dopant is introduced into the exposed silicon followed by an anneal step to and vertically diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region. Upon forming a pair of highly P doped regions on either side of the shallow highly N doped region, the latter functions as a channel stop to arrest charge leakage between the P doped regions due to parasitic FET action at the trench walls.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazene, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

Abstract: Sintering of metal particles at their normal sintering temperature is inhibited by coating the metal particles with an organic material such as polyvinyl butyral, polyvinyl formvar, polyvinyl alcohol, polyacrylonitrile epoxies, urethanes and cross-linked polyvinyl butyral. The organic coating serves as a barrier preventing physical contact between metal particles during the initial phase of the sintering cycle and degrades into a carbonaceous coating followed by volatilization during the intermediate phase of the cycle permitting coalescence of the metal particles into a dense mass along with the coalescence of the glass-ceramic particles. Co-sintering of the metal particles and the glass-ceramic particles with the aid of the organic coating results in a hermetic multi-layer glass ceramic substrate free of dimensional stability problems without deleteriously affecting the electrical conductivity of the metal conductor pattern.

Abstract: Disclosed is a submicron wide single crystal silicon structure protruding from a monolithic silicon body. This three-dimensional structure includes lower section of a first (N) conductivity type and an upper section of a second (P) conductivity type. The upper section consisting of narrow top and bottom portions separated by a relatively wide middle portion, constitutes the silicon material from which various active or passive integrated circuit devices may be fabricated. For example, in the case of an NPN transistor, the central region of the middle portion constitutes the base region, the emitter and collector being embedded in the two outer side regions thereof in a mutually facing relationship. Electrical contacts to the elements of the IC device are established on the top and/or sides of the protruding structure. Owing to its free-standing self-isolated characteristic, dielectric isolation of the IC device is not necessary.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of as layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a chlorocarbon (e.g., CCl.sub.2 F.sub.2, CCl.sub.4 or CCl.sub.3 F), SF.sub.6, O.sub.2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the chlorocarbon to SF6 and the following composition: 1-4% of SF.sub.6, 3-10% of O.sub.2, 74-93% of He and 3-10% of chlorocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.