Abstract: Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate.

Abstract: A mask for structuring surface areas and a method for manufacture thereof. The mask includes at least one metal layer with throughgoing apertures which define the mask pattern and a semiconductor substrate for carrying the metal layer. The semiconductor substrate has throughholes that correspond to the mask pattern. The throughholes in the semiconductor substrate extend from the metal layer-covered surface on the front to at least one tubshaped recess which extends from the other back surface into the semiconductor substrate. Holes are provided in a surface layer in the semiconductor substrate. The surface layer differs in its doping from the rest of the substrate and the holes which are provided in the surface layer have lateral dimensions larger than the apertures in the metal layer so that the metal layer protrudes over the surface layer.

Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. The via stud metallurgy alone is then patterned, preferably by reactive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.

Abstract: Disclosed is a two-stage thermoelectric heat pumping apparatus for heating/cooling an I.C. chip. The first stage is a primary thermoelectric module sandwiched between a base made of a high thermal conductivity material and functioning as a heat source/sink and a heat conductive pad. The second stage is a secondary thermoelectric module sandwiched between the pad and a heat conductive block designed to receive a slotted I.C. chip socket at the top portion thereof and provided with a contact surface such that, upon insertion into the socket, the chip is in direct contact with said contact surface. By passing suitable currents through all the thermoelectric modules heat is pumped, in the heating mode, from the base (source) to the chip and, in the cooling mode, from the chip to the base (sink).

Abstract: Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity.The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.

Abstract: A method of forming planar silicon structures having recessed dielectric isolation oxide regions in which the bird's beak and bird's head associated with the silicon dioxide-silicon nitride dual mask are eliminated. After forming the pad oxide-nitride dual mask, photoresist is used for patterning the active device area and creating a photoresist overhang. Arsenic ions are then implanted and diffused in the isolation regions. Then, using a low (700.degree.-800.degree. C.) temperature wet oxidation, the doped silicon is fully converted to silicon dioxide forming a standard planar structure.A true coplanar structure is obtained by continuing the process by etching the grown oxide and causing the nitride mask to overhang the pad oxide. Then, arsenic ions of a lower energy than before are implanted and diffused in the field regions, which regions are subsequently oxidized at the same low temperature as before forming the final planar structure having completely inset oxide regions.

Abstract: A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-region. The p+ region is coextensive with the thin, memory oxide structure. The binary state of the device is selected by applying a low voltage (e.g., +12v) to the gate and simultaneously applying a suitable voltage to the source and/or drain to induce avalanche breakdown in the channel, or not, to write the device to a "1" state or maintain the device in its original "0" state.

Abstract: Disclosed is a process for forming self-aligned all n.sup.+ -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n.sup.+ dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.

Abstract: A system for loading a DC multiline plasma charge transfer device and for holding charges applied thereto. Each line of the device includes input and transfer electrodes positioned on opposing walls which define a channel confining an ionizable medium. The transfer electrodes comprise adjacent groups of four electrodes with two driven in common with like electrodes of all other lines, and with timing of pulses applied by the common drivers being regular and constant. A common driver is also utilized for the input electrodes of each line while logic control is applied to the input driver and to the other transfer electrodes for each line. With this system and with a minimum of drive electronics, the charges may be shifted to a desired location and in desired patterns along the length of the device. The charges may be held at the desired location by circulating the charges between a set of electrodes at the desired holding location including two commonly driven electrodes.