Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body, there is formed thereon a layered structure of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion of the desired depth obtaining the corresponding portion of the trench having substantially vertical walls. Then by chemical etching the trench is extended to a final portion of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

Abstract: A pulse-operated transistor power amplifier having reduced switching times. The interconnected base electrodes of a pair of complementary transistors (T3, T4) are connected to the collector of a prestage transistor (T1). By a resistor (R2), the base electrodes are also connected to one terminal (+V) of the operating voltage source, to which the collector of one (T4) of the two complementary transistors is also connected. The collector of the other transistor (T3) is connected to the other terminal of the operating voltage source, which is linked with the reference potential. The emitters of the complementary transistors are also connected to each other and, by a capacitor (C1), to the base of the final stage. The voltage changes occurring at the collector when the prestage is switched are transferred by one of the two complementary transistors and the capacitor (C1) to the base of the final stage transistor (T5).

Abstract: Disclosed is a method of treating the surface of a molybdenum mask used for screening a metallized paste pattern to render it smooth and preserve the mask's hardness. The treatment consists of subjecting the mask to a nitridation step by which an ultrathin layer of molybdenum layer is first formed, followed by deposition of a comparatively thick silicon nitride layer thereon. The nitridation step may be accomplished in a plasma deposition system using either forming gas, ammonia or gas mixture of nitrogen and ammonia at a predetermined low temperature and pressure. The silicon nitride deposition may be accomplished in the same system at the same temperature and pressure by substituting the gas utilized to form the molybdenum nitride with a gaseous mixture of silane and one of nitrogen and ammonia.

Abstract: Disclosed is a method of forming a slurry for casting into ceramic green sheets. Starting from selected quantities of a solvent, plasticizer, polymeric binder material, frit and aluminum oxide, a low viscosity pre-mix is formed by combining predetermined portions of the solvent and binder material and all of the plasticizer. The remaining portions of the solvent and binder material are combined into a post-mix. Next, the pre-mix and frit are milled in a ball mill. Then the aluminum oxide is added to the ball mill in steps using predetermined portions and milled for predetermined periods of time to achieve the desired degree of aluminum oxide deagglomeration and particle packing density. Finally, the post-mix is added to the ball mill and milled to obtain the final slurry.

Abstract: Disclosed is a RIE apparatus wherein the anode (maintained at ground potential) is composed of a three-plate configuration and is disposed in parallel relationship with the cathode plate. The top and middle plates of the anode have small gas pump-out holes and are affixed to the chamber walls below the pump-out port to form a high pressure baffle chamber. A gas ring interposed between the top and middle anode plates permits uniform diffusion of etchant species into the reaction volume. The third plate (plasma potential reduction plate -PPRP) of the anode is flexibly attached to the middle plate and contains a large number of large holes compared to those in the top and middle plates. The minimum size of the holes in the PPRP is twice the plasma dark space to permit the plasma formed in the reaction volume below the PPRP to be sustained thereabove, thereby increasing the ratio of the grounded area to the cathode area to which the plasma is exposed.

Abstract: Disclosed is a dumbbell-shaped resistor structure fabricated in a semiconductor substrate for determining the resistivity of the intrinsic base of a polysilicon base transistor. The structure includes an n-doped base region having two large parts separated by a narrow part, resembling a flattened dumbbell, each of which extends into the substrate. A p-type emitter region extends a distance into a portion of the narrow and the second large parts of the base region. An n-type reach-through region extends from the emitter region through the base region electrically isolating a portion of the narrow and second large parts of the base region from the remainder of the base region and forming an electrically continuous p-type path between the first large part of the base region and the portion of the second large part within the reach-through region.

Abstract: A method of making trenches having substantially vertical sidewalls in a silicon substrate using a three level mask comprising a thick photoresist layer, a silicon nitride layer and a thin photoresist layer. Openings are formed in the thin photoresist layer and silicon nitride layer by reactive ion etching in CF.sub.4. The openings are continued through the thick photoresist by etching in an atmosphere containing oxygen. The exposed surface of the silicon substrate is then etched in a CF.sub.4 atmosphere containing a low concentration of fluorine. Also disclosed is a method of making an electron beam transmission mask wherein the openings are made using the three level mask and reactive ion etching of silicon using the etching technique of the invention.

Abstract: Disclosed is a method of forming a trench pattern in a ceramic green sheet for subsequently filling with a conductive paste resulting in a fully inlaid conductor pattern therefrom. Starting with a green sheet, a high contrast ink drawing of the desired conductor pattern is formed thereon. The drawing may be formed by direct printing on the green sheet or by first printing it on a flexible substrate such as paper and then transferring by xerography to the green sheet. Next, the green sheet is illuminated with an intense noncoherent light source to cause a high degree of absorption of the light energy by the inked areas and volatilization of the green sheet binder material thereunder, thereby forming a trench pattern conforming to the drawn pattern.

Abstract: A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions.

Abstract: Disclosed is a method of forming a precision integrated resistor element on a semiconductor wafer whose resistance value accurately corresponds to its nominal design value. The method comprises forming a resistor body in combination with a test resistor structure by conventional ion implantation or diffusion of suitable dopant in selected regions of the wafer. Then, by measuring the resistance(s) and width(s) of the test structure the variation .DELTA..rho..sub.s in sheet resistance and variation .DELTA.W in width due to process and image tolerances, respectively, are determined. Next, using .DELTA..rho..sub.s and .DELTA.W the adjustment in length .DELTA.L necessary to match the resistance of the resistance element with the nominal design value is calculated. Finally, this information (.DELTA.

Abstract: The method of planarizing polysilicon-filled trenches involves first filling the trenches with an undoped polysilicon until the upper surface is substantially planar. The polycrystalline silicon is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon and leaves the undoped polysilicon untouched in the trenches.

Abstract: Semiconductor wafers are polished with an abrasive slurry which is prepared by dispersing montmorillonite clay in deionized water. The pH of the slurry is adjusted to 9.5 to 12.5 by adding alkali such as NaOH and KOH.

Abstract: Disclosed is a method of making ohmic and/or Schottky barrier contacts to a silicon semiconductor substrate in which before depositing the metal on silicon semiconductor substrates containing integrated circuits which are covered by a mask having contact windows, the metal is initially deposited on freshly cleaned blank silicon semiconductor substrates mounted in the same vacuum chamber. In this manner any traces of oxygen present in the vacuum chamber are chemisorbed by the blank substrate resulting in deposition of a high quality oxide-free metal contacts on the device substrates.

Abstract: This invention concerns method and apparatus for making a mask conforming to a cured MLC substrate. The mask when made may be used to add layers of metallization to the cured substrate by conventional photolithographic techniques. The method and apparatus feature use of the cured substrate itself to pattern the mask. Particularly, the substrate is aligned with the unpatterned mask and the image of the substrate transferred to the mask such that once patterned, the mask may subsequently be realigned with the substrate. In preferred form, a system of notches and grooves are used to align the substrate and mask and a lens system used to transfer the substrate image to the mask. The invention also includes method and apparatus for making an improved MLC substrate. The improvement is characterized by the use of photolithographic techniques to add successive layers of metallization to the cured substrate.

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure.

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

Abstract: Disclosed is an automatic self-adjusting CCD activated video camera circuit for adjusting the various CCD channel offset and gain values to the desired levels by utilizing the channels' digitized internal black and white references. Two identical feedback loops are used for offset and gain adjustment, respectively. In the gain/offset adjust loop, the white/black reference is compared to a desired gain/offset set by jumpers or switches on the video camera board. A difference in these values causes a corresponding 10 bit counter to increase or decrease its value. The digital counter value is converted to an analog signal and is used to optimally modify the channel gain/offset.

Abstract: The local state of polarization of a light wave field is determined by measuring the radiation transmitted by one or several polarizers with three different azimuth angles. A modified TV camera is used having its usually provided tri-color filters replaced by polarization filters whose azimuth angles differ from each other by 60.degree. respectively. On a connected color monitor, the local polarization state can be concluded from the local brightness, the hue, and the saturation. The polarization camera can preferably be used for ellipsometric measurings, in an interferometric system for surface topography, and in interferometric holography. The display of the polarization state of the color monitor can be supplemented by electronic means, e.g. emphasizing points having the same state of polarization.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.