Abstract: For compensating scattering losses of electrons in photoresists (proximity effect) which influence electron beam lithography by altering the pattern geometry it is suggested to expose selected partial areas of a pattern to an additional irradiation dosage in a second exposure step. For that purpose, a specific mask with corresponding correction openings can be used which is applied with the same, or with a different electron beam intensity. In a particularly advantageous manner the correction of the proximity effect can be achieved when complementary masks are used; the correction openings for the partial areas of the one complementary mask are arranged in the other complementary mask. The proximity effect is then corrected without an additional exposure step.

Abstract: Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation.

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

Abstract: Disclosed is a method of etching a metallized substrate by excimer laser radiation. The substrate is exposed to a selected gas, e.g., a halogen gas, which spontaneously reacts with the metal forming a solid reaction product layer on the metal by a partial consumption of the metal. A beam of radiation from an excimer laser, e.g. XeF laser operating at a wavelength of 351 nm or XeCl laser at 308 nm or KrF laser at 248 nm or KrCl laser at 222 nm or ArF laser at 193 nm or F.sub.2 laser at 157 nm, is applied to the reaction product in a desired pattern to vaporize the reaction product and thereby selectively etch the metal with a high resolution.

Abstract: Disclosed is a method of etching a metallized substrate by laser radiation. The substrate is exposed to a selected gas which spontaneously reacts with the metal forming a solid reaction product with the metal by a partial consumption of the metal. A beam of radiation of a wavelength suitable for absorption by the reaction product and/or by the metal thereunder is applied in a desired pattern to vaporize the reaction product and thereby selectively etch the metal.

Abstract: Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate.In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base.

Abstract: Disclosed is an on-chip, dual polarity high voltage multiplier circuit consisting of a main high positive voltage multiplier and high negative voltage multiplier and an auxiliary high negative voltage multiplier coupled to the main multipliers to prevent turning on of parasitic transistors associated with the MOS diodes of the main multipliers and thereby extend the operating temperature range to 150.degree. C. and improve the fall time of the dual polarity multiplier. The auxiliary multiplier may be located in a common p-well with the main positive and negative multipliers or with the main negative multiplier and its output voltage is connected to this common well.

Abstract: Disclosed is an apparatus and method for etching a glass substrate by laser induced dry etching. The apparatus features a housing including a vacuum chamber for receiving the substrate; a vacuum pump coupled to the chamber for evacuating the chamber; a gas source coupled to the chamber for supplying a halogen base gas which is capable of wetting the substrate surface and forming a glass etching specie when activated; a laser source for transmitting a light beam of predetermined wavelength and intensity through the gas; and a mask optically coupled to the laser source for patterning the light beam and also coupled to the chamber so that the light patterned by the mask may fall upon the substrate causing excitation thereof and activation of an etch specie for etching the substrate in conformity with the patterned light.

Abstract: This invention concerns method and apparatus for making a mask conforming to a cured MLC substrate. The mask when made may be used to add layers of metallization to the cured substrate by conventional photolithographic techniques. The method and apparatus feature use of the cured substrate itself to pattern the mask. Particularly, the substrate is aligned with the unpatterned mask and the image of the substrate transferred to the mask such that once patterned, the mask may subsequently be realigned with the substrate. In preferred form, a system of notches and grooves are used to align the substrate and mask and a lens system used to transfer the substrate image to the mask. The invention also includes method and apparatus for making an improved MLC substrate. The improvement is characterized by the use of photolithographic techniques to add successive layers of metallization to the cured substrate.

Abstract: Disclosed is an essentially on-chip switching power supply circuit for generating from a single 5 volt power supply high positive and/or low negative voltages of the order of .+-.25 or more. The circuit consists of a pulse generator which alternately activates a positive rail voltage circuit and a negative rail voltage circuit. The positive/negative rail voltage circuit consists of a positive/negative electronic switch in series with a positive/negative voltage generator having an output terminal where the required positive/negative voltage output is generated. The positive/negative voltage generator consists of an inductor and output capacitor coupled together via a rectifying diode.

Abstract: A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.

Abstract: A metal oxide coating is applied between the conductive base and the magnesium oxide dielectric of the input and/or erase electrode(s) in a plasma display device to prevent break-down of the dielectric.

Abstract: The true electrical channel length of a surface FET is determined by obtaining individual electron-beam-induced-current signal traces of source and drain junctions, thus eliminating the coupling effect of the two junctions. A reliable mask is formed as a function of the measured peak-to-peak distance subtracted by the depletion width.

Abstract: For read-only storages and in particular for PLA applications, improved coupling elements together with an associated personalization scheme permit the storing of at least two memory (or logic) connection patterns selectable independently of each other. Quick electrical switching between at least two functional modes in the same storage array, is also provided. One device field effect transistor (FET) cells with specific gate configurations depending on the respective personalization state are used as coupling elements. For instance, in a two-fold personalization permanent storage, the coupling elements consist of FETs with two gate sections provided one beside the other. For a connection to be established in only one of the two possible functions at the respective crosspoint, one of the gate sections is connected to the control line provided for the functional selection. The remaining gate section is connected to the associated input line.

Abstract: Disclosed is a composite pallet for a reactive ion etching system consisting of an upper surface made of an insulative material, such as, silicon having therein a plurality of recessed pockets for holding the wafers to be etched and a bottom surface made of conductive material, such as, aluminum for electrically and thermally communicating the wafers with the cathode. The pallet diameter is larger than that of the cathode, but due to the conductive bottom surface the cathode is effectively extended over the entire pallet diameter. Such an arrangement provides excellent etch uniformity over all portions of the pallet.

Abstract: A process for forming memory quality silicon dioxide and silicon nitride dual-dielectric structures in the same LPCVD furnace system by: forming the silicon dioxide at atmospheric pressure at a temperature of 700.degree.-850.degree. using dry oxygen; heat treating the silicon dioxide layer in ammonia; and forming silicon nitride at 400-600 millitorr and 700.degree.-850.degree. C. using dichlorosilane and ammonia. Optionally, a dielectric layer of silicon oxynitride can be formed on the oxide by using N.sub.2 O, ammonia and dichlorosilane obtaining a memory device with improved retention and endurance.

Abstract: Push-pull driver with reduced noise generation resulting from driver switching. A further transistor is arranged between the driver output transistor (which becomes conductive at the low output level) and the chip ground line. Its base is connected to a reference voltage source the other pole of which is connected to the ground plane of the circuit card to which the corresponding semiconductor chip is attached. If a noise voltage is generated on the chip ground line, the emitter potential of the further transistor is pulled up. As its base potential is maintained at a fixed value by the applied reference potential, this transistor becomes less conductive. As a result, the rate of current change in the output stage is reduced. The slowed down current rise, leads to a reduced noise voltage developing on the common chip ground line.

Abstract: A multilevel metallurgy is formed on a dielectric body, particularly a multilayer ceramic (MLC) body. The interconnection lines and via studs are formed as an integral structure from a blanket metal layer thus eliminating the interface between the via pad and via stud.

Abstract: For compensating scattering losses of electrons in photoresists (proximity effect) which influence electron beam lithography by altering the pattern geometry it is suggested to expose selected partial areas of a pattern to an additional irradiation dosage in a second exposure step. For that purpose, a specific mask with corresponding correction openings can be used which is applied with the same, or with a different electron beam intensity. In a particularly advantageous manner the correction of the proximity effect can be achieved when complementary masks are used; the correction openings for the partial areas of the one complementary mask are arranged in the other complementary mask. The proximity effect is then corrected without an additional exposure step.

Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.