Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.

Abstract: A semiconductor memory device comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of the planes on the basis of a result, obtained by comparing the sensed data of the flag cells of the planes, and the sensed data of the flag cells, and a microcontroller configured to control the page buffer units, wherein the page buffer units read least significant bit (LSB) data of the planes or both the least significant bit (LSB) data and most significant bit (MSB) data on the basis of the determination of the flag cell data detection circuit.

Abstract: A connection system for connecting external devices to specified locations on a marine seismic streamer. Inner collars having raised bosses are clamped to the cable at specified locations along its length. Each inner collar forms a circular race encircling the cable. An external device is attached to a pair of cuffs in the form of C-shaped cylindrical rings each with a circular inner surface. A gap in the ring interrupts the inner surface. The width of the gap is greater than the diameter of the bosses so that the cuffs may be slid onto the collars when the gaps are aligned with the bosses. The bosses are circumferentially offset when the cable is in its normal operating state to lock the cuff and the external device to the collars. The cuffs and the external device can be installed on or removed from the cable by twisting the cable to align the bosses and sliding the cuffs onto or off of the collars. When installed, the cuffs ride on the races to allow the cable to rotate inside the cuffs.

Abstract: A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.

Abstract: An improved system and method for rating subscribers based on wireless subscriber specific credentials. A wireless network operator, or a content/application provider assigns to a subscriber a unique username. For purposes of providing rating or feedback information, the assigned username acts uniquely to identify the subscriber, whose actual identity therefore remains anonymous. The subscriber uses his or her mobile phone to access a mobile telephony network. Evaluators may offer feedback or ratings of the subscriber using the internet.

Abstract: Techniques for dynamically selecting warm-up time for a wireless device operating in the idle mode are described. At each active interval, conditions affecting warm-up of the wireless device at a next active interval are determined. The conditions may pertain to channel conditions, operating conditions, and/or hardware configuration. A warm-up time is selected based on the determined conditions. A wake-up time for the next active interval is determined based on the selected warm-up time. The wireless device then goes to sleep until the wake-up time. In one scheme, the strongest pilot acquired in each active interval is identified, and its pilot strength is averaged to obtain an average pilot strength. The average pilot strength is compared against at least one threshold, and one of at least two possible time durations is selected for the warm-up time based on the comparison result.

Abstract: An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by performing an operation on the first impedance code according to a setting value, and a second code generation unit configured to generate a second impedance code based on the modified impedance code.

Abstract: The access terminal is configured to wirelessly send to a data system a request that the data system assign an access terminal identifier (ATI) to the access terminal. The access terminal delays transmission of the request until after a user of the access terminal has employed the access terminal to request a packet data service from the data system. In some instances, the data system is an Evolution, Data Only (EV-DO) system and the access terminal identifier (ATI) is a Unicast Access Terminal Identifier (UATI) generated by the Evolution, Data Only (EV-DO) system.

Abstract: Disclosed is a power assembly for supplying electrical power to 4-20 mA 2-wire field devices, including HART-enabled, short run Profibus PA, and Foundation Fieldbus protocols. A preferred embodiment of the power assembly is designed to simplify the testing, troubleshooting, and configuration of HART 2-wire field devices. The disclosed device is compatible with hand-held or PC-based configuration software, and utilizes the available power from the USB port of a laptop, or any other compatible source of low-voltage DC. An internal circuit converts the low voltage DC to 24-volt DC to provide 2-wire power for the field devices. The power supply includes the necessary network communication load and/or resistance and may provide a quick modem/network interface and/or milliamp meter connection. All the necessary connections to the 2-wire field device are made with a single pair of quick-disconnect fittings.

Abstract: There is provided a repeating system for cancellation of a feedback interference signal, including: a PA (Power Amplifier) for power-amplifying an output signal; a feedback ICS (Interference Cancellation System) for canceling a feedback interference signal and detecting a residual error; a pre-distorter for compensating for an error of the PA by applying pre-distortion and compensating for the residual error by using information on the residual error detected by the feedback ICS to linearize the characteristic of the PA; and a control unit for controlling the feedback ICS and the pre-distorter.

Abstract: A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.

Abstract: A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.

Abstract: An accumulation-and-release conveyor using a roller belt with rollers arranged to rotate in the direction of belt travel. The rollers extend through the thickness of the belt. A movable stop is positioned along the carryway just downstream of a bearing surface that is movable into and out of contact with the rollers. When the bearing surface is out of contact with the rollers, they are freely rotatable; when the bearing surface contacts the rollers, they roll on the bearing surface to propel articles in the direction of belt travel. The stop is selectively moved between a blocking position preventing articles from passing and accumulating them with low back line pressure on the freely rotatable rollers and a release position allowing articles to pass to the accumulation zone where they are propelled forward and separated from each other by the rotation of the rollers rolling on the bearing surface.

Abstract: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.

Abstract: In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient decoding operation for selecting a repair target address, a test operation of enabling only a word line corresponding to a cell coupled to a bit line or a bit line bar is stably performed.

Abstract: A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process.

Abstract: A resistive memory device includes: a bottom electrode formed over a substrate; and an insulation layer having a hole structure formed over the substrate structure. Herein, the hole structure exposes the bottom electrode, has sidewalls of positive slope, and has a bottom width equal to or smaller than a width of the bottom electrode; a resistive layer formed over the hole structure; and an upper electrode formed over the resistive layer.

Abstract: A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.