Patents Represented by Attorney T

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  • Spectrometer with adjustable-deflector-controlled alignment for optical coherence tomography
    Patent number: 8049886
    Abstract: A spectrometer is presented that can include a spectrally dispersive optical element to spectrally disperse a received light, a leveraged-optics adjustable deflector to adjustably deflect the spectrally dispersed light, and a detector array to receive the spectrally dispersed and adjustably deflected light. The received light can include an interference beam combined from a returned image beam and a reference beam in a Spectral Domain Optical Coherence Tomograph. The detector array can include a linear sensor array. The leveraged-optics adjustable deflector can include an optical element with an adjustable transmissive property or an adjustable reflective property, wherein the adjustable deflector is adjustable by a mechanical adjustment being optically leveraged into a smaller optical adjustment.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: November 1, 2011
    Assignee: Alcon LenSx, Inc.
    Inventor: Ferenc Raksi
  • Integrated circuit
    Patent number: 8049554
    Abstract: An integrated circuit includes a first internal voltage generating unit configured to receive an external power and to generate a first internal voltage, and a second internal voltage generating unit configured to receive the first internal voltage, and to generate a second internal voltage having an absolute value of a target voltage level that is less than an absolute value of the first internal voltage, wherein the second internal voltage generating unit is initially enabled at a later time than the first internal voltage generating unit is initially enabled.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Hwan Kim
  • Semiconductor memory device
    Patent number: 8050118
    Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Whan Kim, Seok-Cheol Yoon
  • Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same
    Patent number: 8050136
    Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park
  • Snap-in tire valve
    Patent number: 8047068
    Abstract: A snap-in tire pressure monitoring system having a valve that deforms to form an annular sealing surface around an opening in a tire rim. A sensor housing having electronics components configured to sense conditions within the tire may be attached to the valve. Data collected by the components may be wireless transmitted for further processing.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: November 1, 2011
    Assignee: Schrader Electronics, Inc.
    Inventors: Lawrence W. Hamm, Michael A. Uleski
  • Semiconductor memory device
    Patent number: 8050127
    Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joong-Ho Lee
  • Cured in place pipe liner
    Patent number: 8047238
    Abstract: A liner for repairing damaged pipes, such as underground sewer or gas pipes is disclosed. The liner comprises a TPU coating on a fibrous mat of non-woven fabric. The TPU coating is a high heat resistance polyester TPU which allows an epoxy resin/amine to be saturated in the non-woven fabric and the cure initiated by the use of steam or hot water. The cured epoxy resin converts the liner from a flexible state to a rigid state as the liner is cured in place inside the pipe. The TPU containing liner may also be used with thermoset resins other than epoxy resins, such as polyester resins and vinyl ester resins.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: November 1, 2011
    Assignee: Lubrizol Advanced Materials, Inc.
    Inventors: Robert J. Wiessner, Donald A. Meltzer
  • Lightweight combat helmet
    Patent number: 8046845
    Abstract: A lightweight combat helmet has a rigid helmet shell with first and second flexible and fluid impermeable receptacles nested within the helmet shell. The first receptacle is filled with structures and substances that alter a trajectory of an incoming projectile. When filled, the second receptacle conforms to a wearer's head.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 1, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Felipe Garcia, Robert Woodall, Chris Doyle, Greg Reitmeyer
  • Method for fabricating vertical channel type nonvolatile memory device
    Patent number: 8048743
    Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Moon-Sig Joo, Kwon Hong, Sun-Hwan Hwang
  • Parallel-to-serial conversion circuit and method thereof
    Patent number: 8049649
    Abstract: A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jinyeong Moon
  • Delay locked loop circuit
    Patent number: 8049544
    Abstract: A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam-Pyo Hong, Jin-Youp Cha
  • Method of programming nonvolatile memory device
    Patent number: 8050103
    Abstract: In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: You Sung Kim, Byung Ryul Kim
  • Fuse apparatus for controlling built-in self stress and control method thereof
    Patent number: 8050122
    Abstract: A fuse apparatus for controlling a built-in self stress unit includes a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record an operation state of the built-in self stress according to the one-cycle end signal. A method for controlling a built-in self stress includes repeatedly generating any stress test mode, in a test mode counting the generated stress test pattern, and activating a cycle end signal when a counting value reaches a predetermined value, and recording an operation state of the built-in self stress in a fuse on the basis of the counted value.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Il Chung
  • Apparatus for generating a voltage and non-volatile memory device having the same
    Patent number: 8050099
    Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: In Soo Wang, Yu Jong Noh, Lee Hyun Kwon, Bon Kwang Koo
  • Automatic detection of separators for compression
    Patent number: 8051060
    Abstract: A method that accepts a data file, iteratively tests different information units as record delimiters and field delimiters, and chooses as the data files record delimiter, R, and field delimiter, F, the information units that result in the lowest generalized entropy that is computed on fields created by use of the chosen delimiter pair R,F.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 1, 2011
    Inventors: Kiem-Phong Vo, Subhabrata Sen
  • Memory device having latch for charging or discharging data input/output line
    Patent number: 8050110
    Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Jin Byeon, Beom-Ju Shin
  • Internal voltage generator of semiconductor device
    Patent number: 8049552
    Abstract: An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Jin Byeon
  • Program method of nonvolatile memory device
    Patent number: 8050098
    Abstract: A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Je Park
  • Surface ornamentation for a container
    Patent number: D647796
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 1, 2011
    Assignee: The Procter & Gamble Company
    Inventors: Doug Sovonick, Rob Anthony
  • Surface ornamentation for a container
    Patent number: D647797
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 1, 2011
    Assignee: The Procter & Gamble Company
    Inventors: Doug Sovonick, Rob Anthony